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All RISC-V platforms have a single HW IPI provided by the INTC local interrupt controller. The HW method to trigger INTC IPI can be through external irqchip (e.g. RISC-V AIA), through platform specific device (e.g. SiFive CLINT timer), or through firmware (e.g. SBI IPI call). To support multiple IPIs on RISC-V, add a generic IPI multiplexing mechanism which help us create multiple virtual IPIs using a single HW IPI. This generic IPI multiplexing is inspired by the Apple AIC irqchip driver and it is shared by various RISC-V irqchip drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Hector Martin <marcan@marcan.st> Tested-by: Hector Martin <marcan@marcan.st> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20230103141221.772261-4-apatel@ventanamicro.com
22 lines
825 B
Makefile
22 lines
825 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-y := irqdesc.o handle.o manage.o spurious.o resend.o chip.o dummychip.o devres.o
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obj-$(CONFIG_IRQ_TIMINGS) += timings.o
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ifeq ($(CONFIG_TEST_IRQ_TIMINGS),y)
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CFLAGS_timings.o += -DDEBUG
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endif
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obj-$(CONFIG_GENERIC_IRQ_CHIP) += generic-chip.o
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obj-$(CONFIG_GENERIC_IRQ_PROBE) += autoprobe.o
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obj-$(CONFIG_IRQ_DOMAIN) += irqdomain.o
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obj-$(CONFIG_IRQ_SIM) += irq_sim.o
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obj-$(CONFIG_PROC_FS) += proc.o
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obj-$(CONFIG_GENERIC_PENDING_IRQ) += migration.o
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obj-$(CONFIG_GENERIC_IRQ_MIGRATION) += cpuhotplug.o
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obj-$(CONFIG_PM_SLEEP) += pm.o
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obj-$(CONFIG_GENERIC_MSI_IRQ) += msi.o
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obj-$(CONFIG_GENERIC_IRQ_IPI) += ipi.o
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obj-$(CONFIG_GENERIC_IRQ_IPI_MUX) += ipi-mux.o
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obj-$(CONFIG_SMP) += affinity.o
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obj-$(CONFIG_GENERIC_IRQ_DEBUGFS) += debugfs.o
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obj-$(CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR) += matrix.o
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