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Transactional Memory was removed from the architecture in ISA v3.1. For threads running in P8/P9 compatibility mode on P10 a synthetic TM implementation is provided. In this implementation, tbegin. always sets cr0 eq meaning the abort handler is always called. This is not an issue as users of TM are expected to have a fallback non transactional way to make forward progress in the abort handler. The TEXASR indicates if a transaction failure is due to a synthetic implementation. Some of the TM self tests need a non-degenerate TM implementation for their testing to be meaningful so check for a synthetic implementation and skip the test if so. Signed-off-by: Jordan Niethe <jniethe5@gmail.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20210729041317.366612-2-jniethe5@gmail.com
133 lines
2.7 KiB
C
133 lines
2.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2015, Michael Ellerman, IBM Corp.
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*/
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#ifndef _SELFTESTS_POWERPC_TM_TM_H
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#define _SELFTESTS_POWERPC_TM_TM_H
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#include <stdbool.h>
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#include <asm/tm.h>
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#include "utils.h"
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#include "reg.h"
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#define TM_RETRIES 100
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static inline bool have_htm(void)
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{
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#ifdef PPC_FEATURE2_HTM
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return have_hwcap2(PPC_FEATURE2_HTM);
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#else
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printf("PPC_FEATURE2_HTM not defined, can't check AT_HWCAP2\n");
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return false;
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#endif
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}
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static inline bool have_htm_nosc(void)
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{
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#ifdef PPC_FEATURE2_HTM_NOSC
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return have_hwcap2(PPC_FEATURE2_HTM_NOSC);
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#else
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printf("PPC_FEATURE2_HTM_NOSC not defined, can't check AT_HWCAP2\n");
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return false;
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#endif
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}
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/*
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* Transactional Memory was removed in ISA 3.1. A synthetic TM implementation
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* is provided on P10 for threads running in P8/P9 compatibility mode. The
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* synthetic implementation immediately fails after tbegin. This failure sets
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* Bit 7 (Failure Persistent) and Bit 15 (Implementation-specific).
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*/
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static inline bool htm_is_synthetic(void)
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{
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int i;
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/*
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* Per the ISA, the Failure Persistent bit may be incorrect. Try a few
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* times in case we got an Implementation-specific failure on a non ISA
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* v3.1 system. On these systems the Implementation-specific failure
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* should not be persistent.
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*/
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for (i = 0; i < TM_RETRIES; i++) {
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asm volatile(
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"tbegin.;"
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"beq 1f;"
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"tend.;"
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"1:"
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:
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:
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: "memory");
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if ((__builtin_get_texasr() & (TEXASR_FP | TEXASR_IC)) !=
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(TEXASR_FP | TEXASR_IC))
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break;
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}
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return i == TM_RETRIES;
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}
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static inline long failure_code(void)
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{
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return __builtin_get_texasru() >> 24;
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}
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static inline bool failure_is_persistent(void)
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{
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return (failure_code() & TM_CAUSE_PERSISTENT) == TM_CAUSE_PERSISTENT;
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}
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static inline bool failure_is_syscall(void)
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{
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return (failure_code() & TM_CAUSE_SYSCALL) == TM_CAUSE_SYSCALL;
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}
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static inline bool failure_is_unavailable(void)
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{
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return (failure_code() & TM_CAUSE_FAC_UNAV) == TM_CAUSE_FAC_UNAV;
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}
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static inline bool failure_is_reschedule(void)
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{
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if ((failure_code() & TM_CAUSE_RESCHED) == TM_CAUSE_RESCHED ||
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(failure_code() & TM_CAUSE_KVM_RESCHED) == TM_CAUSE_KVM_RESCHED ||
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(failure_code() & TM_CAUSE_KVM_FAC_UNAV) == TM_CAUSE_KVM_FAC_UNAV)
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return true;
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return false;
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}
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static inline bool failure_is_nesting(void)
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{
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return (__builtin_get_texasru() & 0x400000);
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}
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static inline int tcheck(void)
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{
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long cr;
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asm volatile ("tcheck 0" : "=r"(cr) : : "cr0");
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return (cr >> 28) & 4;
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}
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static inline bool tcheck_doomed(void)
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{
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return tcheck() & 8;
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}
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static inline bool tcheck_active(void)
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{
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return tcheck() & 4;
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}
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static inline bool tcheck_suspended(void)
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{
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return tcheck() & 2;
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}
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static inline bool tcheck_transactional(void)
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{
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return tcheck() & 6;
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}
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#endif /* _SELFTESTS_POWERPC_TM_TM_H */
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