mirror of
https://github.com/torvalds/linux
synced 2024-10-17 08:46:50 +00:00
137d105d50
On OMAP4 SOC, intecronnects has many write buffers in the async bridges and they need to be drained before CPU enters into standby state. Patch 'OMAP4: PM: Add CPUX OFF mode support' added CPU PM support but OMAP errata i688 (Async Bridge Corruption) needs to be taken care to avoid issues like system freeze, CPU deadlocks, random crashes with register accesses, synchronisation loss on initiators operating on both interconnect port simultaneously. As per the errata, if a data is stalled inside asynchronous bridge because of back pressure, it may be accepted multiple times, creating pointer misalignment that will corrupt next transfers on that data path until next reset of the system (No recovery procedure once the issue is hit, the path remains consistently broken). Async bridge can be found on path between MPU to EMIF and MPU to L3 interconnect. This situation can happen only when the idle is initiated by a Master Request Disconnection (which is trigged by software when executing WFI on CPU). The work-around for this errata needs all the initiators connected through async bridge must ensure that data path is properly drained before issuing WFI. This condition will be met if one Strongly ordered access is performed to the target right before executing the WFI. In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. IO barrier ensure that there is no synchronisation loss on initiators operating on both interconnect port simultaneously. Thanks to Russell for a tip to conver assembly function to C fuction there by reducing 40 odd lines of code from the patch. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Richard Woodruff <r-woodruff2@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
507 lines
11 KiB
C
507 lines
11 KiB
C
/*
|
|
* linux/arch/arm/mach-omap2/io.c
|
|
*
|
|
* OMAP2 I/O mapping code
|
|
*
|
|
* Copyright (C) 2005 Nokia Corporation
|
|
* Copyright (C) 2007-2009 Texas Instruments
|
|
*
|
|
* Author:
|
|
* Juha Yrjola <juha.yrjola@nokia.com>
|
|
* Syed Khasim <x0khasim@ti.com>
|
|
*
|
|
* Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
#include <linux/module.h>
|
|
#include <linux/kernel.h>
|
|
#include <linux/init.h>
|
|
#include <linux/io.h>
|
|
#include <linux/clk.h>
|
|
#include <linux/omapfb.h>
|
|
|
|
#include <asm/tlb.h>
|
|
|
|
#include <asm/mach/map.h>
|
|
|
|
#include <plat/sram.h>
|
|
#include <plat/sdrc.h>
|
|
#include <plat/serial.h>
|
|
|
|
#include "clock2xxx.h"
|
|
#include "clock3xxx.h"
|
|
#include "clock44xx.h"
|
|
|
|
#include "common.h"
|
|
#include <plat/omap-pm.h>
|
|
#include "voltage.h"
|
|
#include "powerdomain.h"
|
|
|
|
#include "clockdomain.h"
|
|
#include <plat/omap_hwmod.h>
|
|
#include <plat/multi.h>
|
|
#include "common.h"
|
|
|
|
/*
|
|
* The machine specific code may provide the extra mapping besides the
|
|
* default mapping provided here.
|
|
*/
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
static struct map_desc omap24xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L3_24XX_VIRT,
|
|
.pfn = __phys_to_pfn(L3_24XX_PHYS),
|
|
.length = L3_24XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = L4_24XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_24XX_PHYS),
|
|
.length = L4_24XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
#ifdef CONFIG_SOC_OMAP2420
|
|
static struct map_desc omap242x_io_desc[] __initdata = {
|
|
{
|
|
.virtual = DSP_MEM_2420_VIRT,
|
|
.pfn = __phys_to_pfn(DSP_MEM_2420_PHYS),
|
|
.length = DSP_MEM_2420_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = DSP_IPI_2420_VIRT,
|
|
.pfn = __phys_to_pfn(DSP_IPI_2420_PHYS),
|
|
.length = DSP_IPI_2420_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = DSP_MMU_2420_VIRT,
|
|
.pfn = __phys_to_pfn(DSP_MMU_2420_PHYS),
|
|
.length = DSP_MMU_2420_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP2430
|
|
static struct map_desc omap243x_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L4_WK_243X_VIRT,
|
|
.pfn = __phys_to_pfn(L4_WK_243X_PHYS),
|
|
.length = L4_WK_243X_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP243X_GPMC_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP243X_GPMC_PHYS),
|
|
.length = OMAP243X_GPMC_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP243X_SDRC_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP243X_SDRC_PHYS),
|
|
.length = OMAP243X_SDRC_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP243X_SMS_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP243X_SMS_PHYS),
|
|
.length = OMAP243X_SMS_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
#endif
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
static struct map_desc omap34xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L3_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L3_34XX_PHYS),
|
|
.length = L3_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = L4_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_34XX_PHYS),
|
|
.length = L4_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP34XX_GPMC_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP34XX_GPMC_PHYS),
|
|
.length = OMAP34XX_GPMC_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP343X_SMS_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP343X_SMS_PHYS),
|
|
.length = OMAP343X_SMS_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = OMAP343X_SDRC_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP343X_SDRC_PHYS),
|
|
.length = OMAP343X_SDRC_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = L4_PER_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_PER_34XX_PHYS),
|
|
.length = L4_PER_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
{
|
|
.virtual = L4_EMU_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_EMU_34XX_PHYS),
|
|
.length = L4_EMU_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
#if defined(CONFIG_DEBUG_LL) && \
|
|
(defined(CONFIG_MACH_OMAP_ZOOM2) || defined(CONFIG_MACH_OMAP_ZOOM3))
|
|
{
|
|
.virtual = ZOOM_UART_VIRT,
|
|
.pfn = __phys_to_pfn(ZOOM_UART_BASE),
|
|
.length = SZ_1M,
|
|
.type = MT_DEVICE
|
|
},
|
|
#endif
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAPTI816X
|
|
static struct map_desc omapti816x_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L4_34XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_34XX_PHYS),
|
|
.length = L4_34XX_SIZE,
|
|
.type = MT_DEVICE
|
|
},
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
static struct map_desc omap44xx_io_desc[] __initdata = {
|
|
{
|
|
.virtual = L3_44XX_VIRT,
|
|
.pfn = __phys_to_pfn(L3_44XX_PHYS),
|
|
.length = L3_44XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = L4_44XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_44XX_PHYS),
|
|
.length = L4_44XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = OMAP44XX_GPMC_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP44XX_GPMC_PHYS),
|
|
.length = OMAP44XX_GPMC_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = OMAP44XX_EMIF1_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP44XX_EMIF1_PHYS),
|
|
.length = OMAP44XX_EMIF1_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = OMAP44XX_EMIF2_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP44XX_EMIF2_PHYS),
|
|
.length = OMAP44XX_EMIF2_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = OMAP44XX_DMM_VIRT,
|
|
.pfn = __phys_to_pfn(OMAP44XX_DMM_PHYS),
|
|
.length = OMAP44XX_DMM_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = L4_PER_44XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_PER_44XX_PHYS),
|
|
.length = L4_PER_44XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
{
|
|
.virtual = L4_EMU_44XX_VIRT,
|
|
.pfn = __phys_to_pfn(L4_EMU_44XX_PHYS),
|
|
.length = L4_EMU_44XX_SIZE,
|
|
.type = MT_DEVICE,
|
|
},
|
|
#ifdef CONFIG_OMAP4_ERRATA_I688
|
|
{
|
|
.virtual = OMAP4_SRAM_VA,
|
|
.pfn = __phys_to_pfn(OMAP4_SRAM_PA),
|
|
.length = PAGE_SIZE,
|
|
.type = MT_MEMORY_SO,
|
|
},
|
|
#endif
|
|
|
|
};
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP2420
|
|
void __init omap242x_map_common_io(void)
|
|
{
|
|
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
|
|
iotable_init(omap242x_io_desc, ARRAY_SIZE(omap242x_io_desc));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAP2430
|
|
void __init omap243x_map_common_io(void)
|
|
{
|
|
iotable_init(omap24xx_io_desc, ARRAY_SIZE(omap24xx_io_desc));
|
|
iotable_init(omap243x_io_desc, ARRAY_SIZE(omap243x_io_desc));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
void __init omap34xx_map_common_io(void)
|
|
{
|
|
iotable_init(omap34xx_io_desc, ARRAY_SIZE(omap34xx_io_desc));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SOC_OMAPTI816X
|
|
void __init omapti816x_map_common_io(void)
|
|
{
|
|
iotable_init(omapti816x_io_desc, ARRAY_SIZE(omapti816x_io_desc));
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
void __init omap44xx_map_common_io(void)
|
|
{
|
|
iotable_init(omap44xx_io_desc, ARRAY_SIZE(omap44xx_io_desc));
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
|
|
*
|
|
* Sets the CORE DPLL3 M2 divider to the same value that it's at
|
|
* currently. This has the effect of setting the SDRC SDRAM AC timing
|
|
* registers to the values currently defined by the kernel. Currently
|
|
* only defined for OMAP3; will return 0 if called on OMAP2. Returns
|
|
* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
|
|
* or passes along the return value of clk_set_rate().
|
|
*/
|
|
static int __init _omap2_init_reprogram_sdrc(void)
|
|
{
|
|
struct clk *dpll3_m2_ck;
|
|
int v = -EINVAL;
|
|
long rate;
|
|
|
|
if (!cpu_is_omap34xx())
|
|
return 0;
|
|
|
|
dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
|
|
if (IS_ERR(dpll3_m2_ck))
|
|
return -EINVAL;
|
|
|
|
rate = clk_get_rate(dpll3_m2_ck);
|
|
pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
|
|
v = clk_set_rate(dpll3_m2_ck, rate);
|
|
if (v)
|
|
pr_err("dpll3_m2_clk rate change failed: %d\n", v);
|
|
|
|
clk_put(dpll3_m2_ck);
|
|
|
|
return v;
|
|
}
|
|
|
|
static int _set_hwmod_postsetup_state(struct omap_hwmod *oh, void *data)
|
|
{
|
|
return omap_hwmod_set_postsetup_state(oh, *(u8 *)data);
|
|
}
|
|
|
|
static void __init omap_common_init_early(void)
|
|
{
|
|
omap2_check_revision();
|
|
omap_init_consistent_dma_size();
|
|
}
|
|
|
|
static void __init omap_hwmod_init_postsetup(void)
|
|
{
|
|
u8 postsetup_state;
|
|
|
|
/* Set the default postsetup state for all hwmods */
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
postsetup_state = _HWMOD_STATE_IDLE;
|
|
#else
|
|
postsetup_state = _HWMOD_STATE_ENABLED;
|
|
#endif
|
|
omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state);
|
|
|
|
/*
|
|
* Set the default postsetup state for unusual modules (like
|
|
* MPU WDT).
|
|
*
|
|
* The postsetup_state is not actually used until
|
|
* omap_hwmod_late_init(), so boards that desire full watchdog
|
|
* coverage of kernel initialization can reprogram the
|
|
* postsetup_state between the calls to
|
|
* omap2_init_common_infra() and omap_sdrc_init().
|
|
*
|
|
* XXX ideally we could detect whether the MPU WDT was currently
|
|
* enabled here and make this conditional
|
|
*/
|
|
postsetup_state = _HWMOD_STATE_DISABLED;
|
|
omap_hwmod_for_each_by_class("wd_timer",
|
|
_set_hwmod_postsetup_state,
|
|
&postsetup_state);
|
|
|
|
omap_pm_if_early_init();
|
|
}
|
|
|
|
#ifdef CONFIG_ARCH_OMAP2
|
|
void __init omap2420_init_early(void)
|
|
{
|
|
omap2_set_globals_242x();
|
|
omap_common_init_early();
|
|
omap2xxx_voltagedomains_init();
|
|
omap242x_powerdomains_init();
|
|
omap242x_clockdomains_init();
|
|
omap2420_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap2420_clk_init();
|
|
}
|
|
|
|
void __init omap2430_init_early(void)
|
|
{
|
|
omap2_set_globals_243x();
|
|
omap_common_init_early();
|
|
omap2xxx_voltagedomains_init();
|
|
omap243x_powerdomains_init();
|
|
omap243x_clockdomains_init();
|
|
omap2430_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap2430_clk_init();
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Currently only board-omap3beagle.c should call this because of the
|
|
* same machine_id for 34xx and 36xx beagle.. Will get fixed with DT.
|
|
*/
|
|
#ifdef CONFIG_ARCH_OMAP3
|
|
void __init omap3_init_early(void)
|
|
{
|
|
omap2_set_globals_3xxx();
|
|
omap_common_init_early();
|
|
omap3xxx_voltagedomains_init();
|
|
omap3xxx_powerdomains_init();
|
|
omap3xxx_clockdomains_init();
|
|
omap3xxx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap3xxx_clk_init();
|
|
}
|
|
|
|
void __init omap3430_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init omap35xx_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init omap3630_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init am35xx_init_early(void)
|
|
{
|
|
omap3_init_early();
|
|
}
|
|
|
|
void __init ti816x_init_early(void)
|
|
{
|
|
omap2_set_globals_ti816x();
|
|
omap_common_init_early();
|
|
omap3xxx_voltagedomains_init();
|
|
omap3xxx_powerdomains_init();
|
|
omap3xxx_clockdomains_init();
|
|
omap3xxx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap3xxx_clk_init();
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARCH_OMAP4
|
|
void __init omap4430_init_early(void)
|
|
{
|
|
omap2_set_globals_443x();
|
|
omap_common_init_early();
|
|
omap44xx_voltagedomains_init();
|
|
omap44xx_powerdomains_init();
|
|
omap44xx_clockdomains_init();
|
|
omap44xx_hwmod_init();
|
|
omap_hwmod_init_postsetup();
|
|
omap4xxx_clk_init();
|
|
}
|
|
#endif
|
|
|
|
void __init omap_sdrc_init(struct omap_sdrc_params *sdrc_cs0,
|
|
struct omap_sdrc_params *sdrc_cs1)
|
|
{
|
|
omap_sram_init();
|
|
|
|
if (cpu_is_omap24xx() || omap3_has_sdrc()) {
|
|
omap2_sdrc_init(sdrc_cs0, sdrc_cs1);
|
|
_omap2_init_reprogram_sdrc();
|
|
}
|
|
}
|
|
|
|
/*
|
|
* NOTE: Please use ioremap + __raw_read/write where possible instead of these
|
|
*/
|
|
|
|
u8 omap_readb(u32 pa)
|
|
{
|
|
return __raw_readb(OMAP2_L4_IO_ADDRESS(pa));
|
|
}
|
|
EXPORT_SYMBOL(omap_readb);
|
|
|
|
u16 omap_readw(u32 pa)
|
|
{
|
|
return __raw_readw(OMAP2_L4_IO_ADDRESS(pa));
|
|
}
|
|
EXPORT_SYMBOL(omap_readw);
|
|
|
|
u32 omap_readl(u32 pa)
|
|
{
|
|
return __raw_readl(OMAP2_L4_IO_ADDRESS(pa));
|
|
}
|
|
EXPORT_SYMBOL(omap_readl);
|
|
|
|
void omap_writeb(u8 v, u32 pa)
|
|
{
|
|
__raw_writeb(v, OMAP2_L4_IO_ADDRESS(pa));
|
|
}
|
|
EXPORT_SYMBOL(omap_writeb);
|
|
|
|
void omap_writew(u16 v, u32 pa)
|
|
{
|
|
__raw_writew(v, OMAP2_L4_IO_ADDRESS(pa));
|
|
}
|
|
EXPORT_SYMBOL(omap_writew);
|
|
|
|
void omap_writel(u32 v, u32 pa)
|
|
{
|
|
__raw_writel(v, OMAP2_L4_IO_ADDRESS(pa));
|
|
}
|
|
EXPORT_SYMBOL(omap_writel);
|