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synced 2024-09-06 18:01:05 +00:00
![Geert Uytterhoeven](/assets/img/avatar_default.png)
Currently, the DesignWare SPI controller driver supports only host mode.
However, spi2 on the Kendryte K210 SoC supports only target mode,
triggering an error message on e.g. SiPEED MAiXBiT since commit
98d75b9ef2
("spi: dw: Drop default number of CS setting"):
dw_spi_mmio 50240000.spi: error -22: problem registering spi host
dw_spi_mmio 50240000.spi: probe with driver dw_spi_mmio failed with error -22
As spi2 rightfully has no "num-cs" property, num_chipselect is now zero,
causing spi_alloc_host() to fail to register the controller. Before,
the driver silently registered an SPI host controller with 4 chip
selects.
Reject target mode early on and warn the user, getting rid of the
error message.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Damien Le Moal <dlemoal@kernel.org>
Link: https://lore.kernel.org/r/7ae28d83bff7351f34782658ae1bb69cc731693e.1715163113.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>
449 lines
12 KiB
C
449 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Memory-mapped interface driver for DW SPI Core
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*
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* Copyright (c) 2010, Octasic semiconductor.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/scatterlist.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/acpi.h>
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#include <linux/property.h>
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#include <linux/regmap.h>
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#include <linux/reset.h>
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#include "spi-dw.h"
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#define DRIVER_NAME "dw_spi_mmio"
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struct dw_spi_mmio {
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struct dw_spi dws;
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struct clk *clk;
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struct clk *pclk;
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void *priv;
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struct reset_control *rstc;
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};
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#define MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL 0x24
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#define OCELOT_IF_SI_OWNER_OFFSET 4
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#define JAGUAR2_IF_SI_OWNER_OFFSET 6
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#define MSCC_IF_SI_OWNER_MASK GENMASK(1, 0)
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#define MSCC_IF_SI_OWNER_SISL 0
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#define MSCC_IF_SI_OWNER_SIBM 1
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#define MSCC_IF_SI_OWNER_SIMC 2
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#define MSCC_SPI_MST_SW_MODE 0x14
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#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
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#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
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#define SPARX5_FORCE_ENA 0xa4
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#define SPARX5_FORCE_VAL 0xa8
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struct dw_spi_mscc {
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struct regmap *syscon;
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void __iomem *spi_mst; /* Not sparx5 */
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};
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/*
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* Elba SoC does not use ssi, pin override is used for cs 0,1 and
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* gpios for cs 2,3 as defined in the device tree.
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*
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* cs: | 1 0
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* bit: |---3-------2-------1-------0
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* | cs1 cs1_ovr cs0 cs0_ovr
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*/
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#define ELBA_SPICS_REG 0x2468
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#define ELBA_SPICS_OFFSET(cs) ((cs) << 1)
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#define ELBA_SPICS_MASK(cs) (GENMASK(1, 0) << ELBA_SPICS_OFFSET(cs))
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#define ELBA_SPICS_SET(cs, val) \
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((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs))
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/*
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* The Designware SPI controller (referred to as master in the documentation)
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* automatically deasserts chip select when the tx fifo is empty. The chip
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* selects then needs to be either driven as GPIOs or, for the first 4 using
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* the SPI boot controller registers. the final chip select is an OR gate
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* between the Designware SPI controller and the SPI boot controller.
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*/
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static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
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{
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struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
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struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
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struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
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u32 cs = spi_get_chipselect(spi, 0);
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if (cs < 4) {
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u32 sw_mode = MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE;
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if (!enable)
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sw_mode |= MSCC_SPI_MST_SW_MODE_SW_SPI_CS(BIT(cs));
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writel(sw_mode, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
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}
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dw_spi_set_cs(spi, enable);
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}
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static int dw_spi_mscc_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio,
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const char *cpu_syscon, u32 if_si_owner_offset)
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{
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struct dw_spi_mscc *dwsmscc;
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dwsmscc = devm_kzalloc(&pdev->dev, sizeof(*dwsmscc), GFP_KERNEL);
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if (!dwsmscc)
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return -ENOMEM;
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dwsmscc->spi_mst = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(dwsmscc->spi_mst)) {
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dev_err(&pdev->dev, "SPI_MST region map failed\n");
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return PTR_ERR(dwsmscc->spi_mst);
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}
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dwsmscc->syscon = syscon_regmap_lookup_by_compatible(cpu_syscon);
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if (IS_ERR(dwsmscc->syscon))
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return PTR_ERR(dwsmscc->syscon);
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/* Deassert all CS */
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writel(0, dwsmscc->spi_mst + MSCC_SPI_MST_SW_MODE);
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/* Select the owner of the SI interface */
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regmap_update_bits(dwsmscc->syscon, MSCC_CPU_SYSTEM_CTRL_GENERAL_CTRL,
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MSCC_IF_SI_OWNER_MASK << if_si_owner_offset,
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MSCC_IF_SI_OWNER_SIMC << if_si_owner_offset);
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dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
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dwsmmio->priv = dwsmscc;
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return 0;
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}
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static int dw_spi_mscc_ocelot_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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return dw_spi_mscc_init(pdev, dwsmmio, "mscc,ocelot-cpu-syscon",
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OCELOT_IF_SI_OWNER_OFFSET);
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}
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static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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return dw_spi_mscc_init(pdev, dwsmmio, "mscc,jaguar2-cpu-syscon",
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JAGUAR2_IF_SI_OWNER_OFFSET);
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}
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/*
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* The Designware SPI controller (referred to as master in the
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* documentation) automatically deasserts chip select when the tx fifo
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* is empty. The chip selects then needs to be driven by a CS override
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* register. enable is an active low signal.
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*/
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static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)
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{
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struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
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struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
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struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
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u8 cs = spi_get_chipselect(spi, 0);
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if (!enable) {
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/* CS override drive enable */
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regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 1);
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/* Now set CSx enabled */
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regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~BIT(cs));
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/* Allow settle */
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usleep_range(1, 5);
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} else {
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/* CS value */
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regmap_write(dwsmscc->syscon, SPARX5_FORCE_VAL, ~0);
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/* Allow settle */
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usleep_range(1, 5);
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/* CS override drive disable */
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regmap_write(dwsmscc->syscon, SPARX5_FORCE_ENA, 0);
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}
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dw_spi_set_cs(spi, enable);
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}
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static int dw_spi_mscc_sparx5_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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const char *syscon_name = "microchip,sparx5-cpu-syscon";
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struct device *dev = &pdev->dev;
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struct dw_spi_mscc *dwsmscc;
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if (!IS_ENABLED(CONFIG_SPI_MUX)) {
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dev_err(dev, "This driver needs CONFIG_SPI_MUX\n");
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return -EOPNOTSUPP;
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}
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dwsmscc = devm_kzalloc(dev, sizeof(*dwsmscc), GFP_KERNEL);
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if (!dwsmscc)
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return -ENOMEM;
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dwsmscc->syscon =
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syscon_regmap_lookup_by_compatible(syscon_name);
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if (IS_ERR(dwsmscc->syscon)) {
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dev_err(dev, "No syscon map %s\n", syscon_name);
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return PTR_ERR(dwsmscc->syscon);
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}
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dwsmmio->dws.set_cs = dw_spi_sparx5_set_cs;
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dwsmmio->priv = dwsmscc;
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return 0;
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}
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static int dw_spi_alpine_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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dwsmmio->dws.caps = DW_SPI_CAP_CS_OVERRIDE;
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return 0;
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}
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static int dw_spi_pssi_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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dw_spi_dma_setup_generic(&dwsmmio->dws);
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return 0;
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}
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static int dw_spi_hssi_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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dwsmmio->dws.ip = DW_HSSI_ID;
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dw_spi_dma_setup_generic(&dwsmmio->dws);
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return 0;
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}
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static int dw_spi_intel_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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dwsmmio->dws.ip = DW_HSSI_ID;
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return 0;
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}
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/*
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* DMA-based mem ops are not configured for this device and are not tested.
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*/
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static int dw_spi_mountevans_imc_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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/*
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* The Intel Mount Evans SoC's Integrated Management Complex DW
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* apb_ssi_v4.02a controller has an errata where a full TX FIFO can
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* result in data corruption. The suggested workaround is to never
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* completely fill the FIFO. The TX FIFO has a size of 32 so the
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* fifo_len is set to 31.
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*/
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dwsmmio->dws.fifo_len = 31;
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return 0;
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}
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static int dw_spi_canaan_k210_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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/*
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* The Canaan Kendryte K210 SoC DW apb_ssi v4 spi controller is
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* documented to have a 32 word deep TX and RX FIFO, which
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* spi_hw_init() detects. However, when the RX FIFO is filled up to
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* 32 entries (RXFLR = 32), an RX FIFO overrun error occurs. Avoid this
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* problem by force setting fifo_len to 31.
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*/
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dwsmmio->dws.fifo_len = 31;
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return 0;
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}
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static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable)
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{
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regmap_update_bits(syscon, ELBA_SPICS_REG, ELBA_SPICS_MASK(cs),
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ELBA_SPICS_SET(cs, enable));
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}
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static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
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{
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struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
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struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
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struct regmap *syscon = dwsmmio->priv;
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u8 cs;
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cs = spi_get_chipselect(spi, 0);
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if (cs < 2)
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dw_spi_elba_override_cs(syscon, spi_get_chipselect(spi, 0), enable);
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/*
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* The DW SPI controller needs a native CS bit selected to start
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* the serial engine.
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*/
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spi_set_chipselect(spi, 0, 0);
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dw_spi_set_cs(spi, enable);
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spi_set_chipselect(spi, 0, cs);
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}
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static int dw_spi_elba_init(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio)
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{
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struct regmap *syscon;
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syscon = syscon_regmap_lookup_by_phandle(dev_of_node(&pdev->dev),
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"amd,pensando-elba-syscon");
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if (IS_ERR(syscon))
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return dev_err_probe(&pdev->dev, PTR_ERR(syscon),
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"syscon regmap lookup failed\n");
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dwsmmio->priv = syscon;
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dwsmmio->dws.set_cs = dw_spi_elba_set_cs;
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return 0;
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}
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static int dw_spi_mmio_probe(struct platform_device *pdev)
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{
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int (*init_func)(struct platform_device *pdev,
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struct dw_spi_mmio *dwsmmio);
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struct dw_spi_mmio *dwsmmio;
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struct resource *mem;
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struct dw_spi *dws;
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int ret;
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if (device_property_read_bool(&pdev->dev, "spi-slave")) {
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dev_warn(&pdev->dev, "spi-slave is not yet supported\n");
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return -ENODEV;
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}
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dwsmmio = devm_kzalloc(&pdev->dev, sizeof(struct dw_spi_mmio),
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GFP_KERNEL);
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if (!dwsmmio)
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return -ENOMEM;
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dws = &dwsmmio->dws;
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/* Get basic io resource and map it */
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dws->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
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if (IS_ERR(dws->regs))
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return PTR_ERR(dws->regs);
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dws->paddr = mem->start;
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dws->irq = platform_get_irq(pdev, 0);
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if (dws->irq < 0)
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return dws->irq; /* -ENXIO */
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dwsmmio->clk = devm_clk_get_enabled(&pdev->dev, NULL);
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if (IS_ERR(dwsmmio->clk))
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return PTR_ERR(dwsmmio->clk);
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/* Optional clock needed to access the registers */
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dwsmmio->pclk = devm_clk_get_optional_enabled(&pdev->dev, "pclk");
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if (IS_ERR(dwsmmio->pclk))
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return PTR_ERR(dwsmmio->pclk);
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/* find an optional reset controller */
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dwsmmio->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, "spi");
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if (IS_ERR(dwsmmio->rstc))
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return PTR_ERR(dwsmmio->rstc);
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reset_control_deassert(dwsmmio->rstc);
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dws->bus_num = pdev->id;
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dws->max_freq = clk_get_rate(dwsmmio->clk);
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if (device_property_read_u32(&pdev->dev, "reg-io-width",
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&dws->reg_io_width))
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dws->reg_io_width = 4;
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/* Rely on the auto-detection if no property specified */
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device_property_read_u32(&pdev->dev, "num-cs", &dws->num_cs);
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init_func = device_get_match_data(&pdev->dev);
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if (init_func) {
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ret = init_func(pdev, dwsmmio);
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if (ret)
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goto out_reset;
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}
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pm_runtime_enable(&pdev->dev);
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ret = dw_spi_add_host(&pdev->dev, dws);
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if (ret)
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goto out;
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platform_set_drvdata(pdev, dwsmmio);
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return 0;
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out:
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pm_runtime_disable(&pdev->dev);
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out_reset:
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reset_control_assert(dwsmmio->rstc);
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return ret;
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}
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static void dw_spi_mmio_remove(struct platform_device *pdev)
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{
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struct dw_spi_mmio *dwsmmio = platform_get_drvdata(pdev);
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dw_spi_remove_host(&dwsmmio->dws);
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pm_runtime_disable(&pdev->dev);
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reset_control_assert(dwsmmio->rstc);
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}
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static const struct of_device_id dw_spi_mmio_of_match[] = {
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{ .compatible = "snps,dw-apb-ssi", .data = dw_spi_pssi_init},
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{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
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{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
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{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
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{ .compatible = "renesas,rzn1-spi", .data = dw_spi_pssi_init},
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{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_hssi_init},
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{ .compatible = "intel,keembay-ssi", .data = dw_spi_intel_init},
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{
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.compatible = "intel,mountevans-imc-ssi",
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.data = dw_spi_mountevans_imc_init,
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},
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{ .compatible = "microchip,sparx5-spi", dw_spi_mscc_sparx5_init},
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{ .compatible = "canaan,k210-spi", dw_spi_canaan_k210_init},
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{ .compatible = "amd,pensando-elba-spi", .data = dw_spi_elba_init},
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{ /* end of table */}
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};
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MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
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#ifdef CONFIG_ACPI
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static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
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{"HISI0173", (kernel_ulong_t)dw_spi_pssi_init},
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{},
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};
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MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
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#endif
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static struct platform_driver dw_spi_mmio_driver = {
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.probe = dw_spi_mmio_probe,
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.remove_new = dw_spi_mmio_remove,
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.driver = {
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.name = DRIVER_NAME,
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.of_match_table = dw_spi_mmio_of_match,
|
|
.acpi_match_table = ACPI_PTR(dw_spi_mmio_acpi_match),
|
|
},
|
|
};
|
|
module_platform_driver(dw_spi_mmio_driver);
|
|
|
|
MODULE_AUTHOR("Jean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>");
|
|
MODULE_DESCRIPTION("Memory-mapped I/O interface driver for DW SPI Core");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_IMPORT_NS(SPI_DW_CORE);
|