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https://github.com/torvalds/linux
synced 2024-09-06 18:01:05 +00:00
![Jim Liu](/assets/img/avatar_default.png)
The generic_handle_domain_irq() function calls irq_resolve_mapping().
Thus delete a duplicative irq_find_mapping() call
so that a stack trace and an RCU stall will be avoided.
Fixes: c4f8457d17
("gpio: nuvoton: Add Nuvoton NPCM sgpio driver")
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/20240506064244.1645922-1-JJLIU0@nuvoton.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
618 lines
14 KiB
C
618 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Nuvoton NPCM Serial GPIO Driver
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*
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* Copyright (C) 2021 Nuvoton Technologies
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*/
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#include <linux/bitfield.h>
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#include <linux/clk.h>
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#include <linux/gpio/driver.h>
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#include <linux/hashtable.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/spinlock.h>
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#include <linux/string.h>
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#include <linux/units.h>
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#define MAX_NR_HW_SGPIO 64
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#define NPCM_IOXCFG1 0x2A
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#define NPCM_IOXCFG1_SFT_CLK GENMASK(3, 0)
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#define NPCM_IOXCFG1_SCLK_POL BIT(4)
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#define NPCM_IOXCFG1_LDSH_POL BIT(5)
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#define NPCM_IOXCTS 0x28
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#define NPCM_IOXCTS_IOXIF_EN BIT(7)
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#define NPCM_IOXCTS_RD_MODE GENMASK(2, 1)
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#define NPCM_IOXCTS_RD_MODE_PERIODIC BIT(2)
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#define NPCM_IOXCFG2 0x2B
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#define NPCM_IOXCFG2_PORT GENMASK(3, 0)
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#define NPCM_IXOEVCFG_MASK GENMASK(1, 0)
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#define NPCM_IXOEVCFG_FALLING BIT(1)
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#define NPCM_IXOEVCFG_RISING BIT(0)
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#define NPCM_IXOEVCFG_BOTH (NPCM_IXOEVCFG_FALLING | NPCM_IXOEVCFG_RISING)
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#define NPCM_CLK_MHZ (8 * HZ_PER_MHZ)
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#define NPCM_750_OPT 6
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#define NPCM_845_OPT 5
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#define GPIO_BANK(x) ((x) / 8)
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#define GPIO_BIT(x) ((x) % 8)
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/*
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* Select the frequency of shift clock.
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* The shift clock is a division of the APB clock.
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*/
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struct npcm_clk_cfg {
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unsigned int *sft_clk;
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unsigned int *clk_sel;
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unsigned int cfg_opt;
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};
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struct npcm_sgpio {
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struct gpio_chip chip;
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struct clk *pclk;
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struct irq_chip intc;
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raw_spinlock_t lock;
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void __iomem *base;
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int irq;
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u8 nin_sgpio;
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u8 nout_sgpio;
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u8 in_port;
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u8 out_port;
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u8 int_type[MAX_NR_HW_SGPIO];
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};
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struct npcm_sgpio_bank {
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u8 rdata_reg;
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u8 wdata_reg;
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u8 event_config;
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u8 event_status;
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};
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enum npcm_sgpio_reg {
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READ_DATA,
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WRITE_DATA,
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EVENT_CFG,
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EVENT_STS,
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};
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static const struct npcm_sgpio_bank npcm_sgpio_banks[] = {
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{
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.wdata_reg = 0x00,
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.rdata_reg = 0x08,
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.event_config = 0x10,
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.event_status = 0x20,
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},
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{
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.wdata_reg = 0x01,
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.rdata_reg = 0x09,
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.event_config = 0x12,
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.event_status = 0x21,
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},
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{
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.wdata_reg = 0x02,
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.rdata_reg = 0x0a,
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.event_config = 0x14,
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.event_status = 0x22,
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},
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{
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.wdata_reg = 0x03,
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.rdata_reg = 0x0b,
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.event_config = 0x16,
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.event_status = 0x23,
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},
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{
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.wdata_reg = 0x04,
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.rdata_reg = 0x0c,
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.event_config = 0x18,
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.event_status = 0x24,
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},
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{
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.wdata_reg = 0x05,
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.rdata_reg = 0x0d,
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.event_config = 0x1a,
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.event_status = 0x25,
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},
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{
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.wdata_reg = 0x06,
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.rdata_reg = 0x0e,
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.event_config = 0x1c,
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.event_status = 0x26,
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},
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{
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.wdata_reg = 0x07,
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.rdata_reg = 0x0f,
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.event_config = 0x1e,
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.event_status = 0x27,
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},
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};
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static void __iomem *bank_reg(struct npcm_sgpio *gpio,
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const struct npcm_sgpio_bank *bank,
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const enum npcm_sgpio_reg reg)
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{
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switch (reg) {
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case READ_DATA:
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return gpio->base + bank->rdata_reg;
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case WRITE_DATA:
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return gpio->base + bank->wdata_reg;
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case EVENT_CFG:
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return gpio->base + bank->event_config;
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case EVENT_STS:
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return gpio->base + bank->event_status;
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default:
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/* actually if code runs to here, it's an error case */
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dev_WARN(gpio->chip.parent, "Getting here is an error condition");
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return NULL;
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}
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}
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static const struct npcm_sgpio_bank *offset_to_bank(unsigned int offset)
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{
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unsigned int bank = GPIO_BANK(offset);
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return &npcm_sgpio_banks[bank];
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}
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static void npcm_sgpio_irqd_to_data(struct irq_data *d,
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struct npcm_sgpio **gpio,
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const struct npcm_sgpio_bank **bank,
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u8 *bit, unsigned int *offset)
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{
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struct npcm_sgpio *internal;
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*offset = irqd_to_hwirq(d);
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internal = irq_data_get_irq_chip_data(d);
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*gpio = internal;
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*offset -= internal->nout_sgpio;
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*bank = offset_to_bank(*offset);
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*bit = GPIO_BIT(*offset);
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}
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static int npcm_sgpio_init_port(struct npcm_sgpio *gpio)
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{
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u8 in_port, out_port, set_port, reg;
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in_port = GPIO_BANK(gpio->nin_sgpio);
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if (GPIO_BIT(gpio->nin_sgpio) > 0)
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in_port += 1;
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out_port = GPIO_BANK(gpio->nout_sgpio);
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if (GPIO_BIT(gpio->nout_sgpio) > 0)
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out_port += 1;
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gpio->in_port = in_port;
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gpio->out_port = out_port;
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set_port = (out_port & NPCM_IOXCFG2_PORT) << 4 |
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(in_port & NPCM_IOXCFG2_PORT);
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iowrite8(set_port, gpio->base + NPCM_IOXCFG2);
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reg = ioread8(gpio->base + NPCM_IOXCFG2);
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return reg == set_port ? 0 : -EINVAL;
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}
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static int npcm_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset)
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{
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struct npcm_sgpio *gpio = gpiochip_get_data(gc);
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return offset < gpio->nout_sgpio ? -EINVAL : 0;
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}
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static int npcm_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val)
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{
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gc->set(gc, offset, val);
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return 0;
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}
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static int npcm_sgpio_get_direction(struct gpio_chip *gc, unsigned int offset)
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{
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struct npcm_sgpio *gpio = gpiochip_get_data(gc);
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if (offset < gpio->nout_sgpio)
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return GPIO_LINE_DIRECTION_OUT;
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return GPIO_LINE_DIRECTION_IN;
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}
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static void npcm_sgpio_set(struct gpio_chip *gc, unsigned int offset, int val)
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{
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struct npcm_sgpio *gpio = gpiochip_get_data(gc);
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const struct npcm_sgpio_bank *bank = offset_to_bank(offset);
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void __iomem *addr;
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u8 reg = 0;
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addr = bank_reg(gpio, bank, WRITE_DATA);
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reg = ioread8(addr);
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if (val)
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reg |= BIT(GPIO_BIT(offset));
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else
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reg &= ~BIT(GPIO_BIT(offset));
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iowrite8(reg, addr);
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}
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static int npcm_sgpio_get(struct gpio_chip *gc, unsigned int offset)
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{
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struct npcm_sgpio *gpio = gpiochip_get_data(gc);
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const struct npcm_sgpio_bank *bank;
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void __iomem *addr;
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u8 reg;
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if (offset < gpio->nout_sgpio) {
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bank = offset_to_bank(offset);
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addr = bank_reg(gpio, bank, WRITE_DATA);
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} else {
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offset -= gpio->nout_sgpio;
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bank = offset_to_bank(offset);
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addr = bank_reg(gpio, bank, READ_DATA);
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}
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reg = ioread8(addr);
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return !!(reg & BIT(GPIO_BIT(offset)));
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}
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static void npcm_sgpio_setup_enable(struct npcm_sgpio *gpio, bool enable)
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{
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u8 reg;
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reg = ioread8(gpio->base + NPCM_IOXCTS);
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reg = (reg & ~NPCM_IOXCTS_RD_MODE) | NPCM_IOXCTS_RD_MODE_PERIODIC;
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if (enable)
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reg |= NPCM_IOXCTS_IOXIF_EN;
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else
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reg &= ~NPCM_IOXCTS_IOXIF_EN;
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iowrite8(reg, gpio->base + NPCM_IOXCTS);
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}
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static int npcm_sgpio_setup_clk(struct npcm_sgpio *gpio,
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const struct npcm_clk_cfg *clk_cfg)
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{
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unsigned long apb_freq;
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u32 val;
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u8 tmp;
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int i;
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apb_freq = clk_get_rate(gpio->pclk);
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tmp = ioread8(gpio->base + NPCM_IOXCFG1) & ~NPCM_IOXCFG1_SFT_CLK;
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for (i = clk_cfg->cfg_opt-1; i > 0; i--) {
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val = apb_freq / clk_cfg->sft_clk[i];
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if (NPCM_CLK_MHZ > val) {
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iowrite8(clk_cfg->clk_sel[i] | tmp,
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gpio->base + NPCM_IOXCFG1);
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return 0;
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}
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}
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return -EINVAL;
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}
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static void npcm_sgpio_irq_init_valid_mask(struct gpio_chip *gc,
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unsigned long *valid_mask,
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unsigned int ngpios)
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{
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struct npcm_sgpio *gpio = gpiochip_get_data(gc);
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/* input GPIOs in the high range */
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bitmap_set(valid_mask, gpio->nout_sgpio, gpio->nin_sgpio);
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bitmap_clear(valid_mask, 0, gpio->nout_sgpio);
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}
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static void npcm_sgpio_irq_set_mask(struct irq_data *d, bool set)
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{
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const struct npcm_sgpio_bank *bank;
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struct npcm_sgpio *gpio;
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unsigned long flags;
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void __iomem *addr;
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unsigned int offset;
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u16 reg, type;
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u8 bit;
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npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);
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addr = bank_reg(gpio, bank, EVENT_CFG);
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reg = ioread16(addr);
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if (set) {
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reg &= ~(NPCM_IXOEVCFG_MASK << (bit * 2));
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} else {
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type = gpio->int_type[offset];
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reg |= (type << (bit * 2));
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}
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raw_spin_lock_irqsave(&gpio->lock, flags);
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npcm_sgpio_setup_enable(gpio, false);
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iowrite16(reg, addr);
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npcm_sgpio_setup_enable(gpio, true);
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addr = bank_reg(gpio, bank, EVENT_STS);
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reg = ioread8(addr);
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reg |= BIT(bit);
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iowrite8(reg, addr);
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raw_spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static void npcm_sgpio_irq_ack(struct irq_data *d)
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{
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const struct npcm_sgpio_bank *bank;
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struct npcm_sgpio *gpio;
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unsigned long flags;
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void __iomem *status_addr;
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unsigned int offset;
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u8 bit;
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npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);
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status_addr = bank_reg(gpio, bank, EVENT_STS);
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raw_spin_lock_irqsave(&gpio->lock, flags);
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iowrite8(BIT(bit), status_addr);
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raw_spin_unlock_irqrestore(&gpio->lock, flags);
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}
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static void npcm_sgpio_irq_mask(struct irq_data *d)
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{
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npcm_sgpio_irq_set_mask(d, true);
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}
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static void npcm_sgpio_irq_unmask(struct irq_data *d)
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{
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npcm_sgpio_irq_set_mask(d, false);
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}
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static int npcm_sgpio_set_type(struct irq_data *d, unsigned int type)
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{
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const struct npcm_sgpio_bank *bank;
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irq_flow_handler_t handler;
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struct npcm_sgpio *gpio;
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unsigned long flags;
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void __iomem *addr;
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unsigned int offset;
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u16 reg, val;
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u8 bit;
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npcm_sgpio_irqd_to_data(d, &gpio, &bank, &bit, &offset);
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switch (type & IRQ_TYPE_SENSE_MASK) {
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case IRQ_TYPE_EDGE_BOTH:
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val = NPCM_IXOEVCFG_BOTH;
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break;
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case IRQ_TYPE_EDGE_RISING:
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case IRQ_TYPE_LEVEL_HIGH:
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val = NPCM_IXOEVCFG_RISING;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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case IRQ_TYPE_LEVEL_LOW:
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val = NPCM_IXOEVCFG_FALLING;
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break;
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default:
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return -EINVAL;
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}
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if (type & IRQ_TYPE_LEVEL_MASK)
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handler = handle_level_irq;
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else
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handler = handle_edge_irq;
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gpio->int_type[offset] = val;
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raw_spin_lock_irqsave(&gpio->lock, flags);
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npcm_sgpio_setup_enable(gpio, false);
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addr = bank_reg(gpio, bank, EVENT_CFG);
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reg = ioread16(addr);
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reg |= (val << (bit * 2));
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iowrite16(reg, addr);
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npcm_sgpio_setup_enable(gpio, true);
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raw_spin_unlock_irqrestore(&gpio->lock, flags);
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irq_set_handler_locked(d, handler);
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return 0;
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}
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static void npcm_sgpio_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct irq_chip *ic = irq_desc_get_chip(desc);
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struct npcm_sgpio *gpio = gpiochip_get_data(gc);
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unsigned int i, j;
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unsigned long reg;
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chained_irq_enter(ic, desc);
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for (i = 0; i < ARRAY_SIZE(npcm_sgpio_banks); i++) {
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const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i];
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reg = ioread8(bank_reg(gpio, bank, EVENT_STS));
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for_each_set_bit(j, ®, 8)
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generic_handle_domain_irq(gc->irq.domain,
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i * 8 + gpio->nout_sgpio + j);
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}
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chained_irq_exit(ic, desc);
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}
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static const struct irq_chip sgpio_irq_chip = {
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.name = "sgpio-irq",
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.irq_ack = npcm_sgpio_irq_ack,
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.irq_mask = npcm_sgpio_irq_mask,
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.irq_unmask = npcm_sgpio_irq_unmask,
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.irq_set_type = npcm_sgpio_set_type,
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.flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
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GPIOCHIP_IRQ_RESOURCE_HELPERS,
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};
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static int npcm_sgpio_setup_irqs(struct npcm_sgpio *gpio,
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struct platform_device *pdev)
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{
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int rc, i;
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struct gpio_irq_chip *irq;
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rc = platform_get_irq(pdev, 0);
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if (rc < 0)
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return rc;
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gpio->irq = rc;
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npcm_sgpio_setup_enable(gpio, false);
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/* Disable IRQ and clear Interrupt status registers for all SGPIO Pins. */
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for (i = 0; i < ARRAY_SIZE(npcm_sgpio_banks); i++) {
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const struct npcm_sgpio_bank *bank = &npcm_sgpio_banks[i];
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iowrite16(0, bank_reg(gpio, bank, EVENT_CFG));
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iowrite8(0xff, bank_reg(gpio, bank, EVENT_STS));
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}
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irq = &gpio->chip.irq;
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gpio_irq_chip_set_chip(irq, &sgpio_irq_chip);
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irq->init_valid_mask = npcm_sgpio_irq_init_valid_mask;
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irq->handler = handle_bad_irq;
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irq->default_type = IRQ_TYPE_NONE;
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irq->parent_handler = npcm_sgpio_irq_handler;
|
|
irq->parent_handler_data = gpio;
|
|
irq->parents = &gpio->irq;
|
|
irq->num_parents = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int npcm_sgpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct npcm_sgpio *gpio;
|
|
const struct npcm_clk_cfg *clk_cfg;
|
|
int rc;
|
|
u32 nin_gpios, nout_gpios;
|
|
|
|
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
|
|
if (!gpio)
|
|
return -ENOMEM;
|
|
|
|
gpio->base = devm_platform_ioremap_resource(pdev, 0);
|
|
if (IS_ERR(gpio->base))
|
|
return PTR_ERR(gpio->base);
|
|
|
|
clk_cfg = device_get_match_data(&pdev->dev);
|
|
if (!clk_cfg)
|
|
return -EINVAL;
|
|
|
|
rc = device_property_read_u32(&pdev->dev, "nuvoton,input-ngpios",
|
|
&nin_gpios);
|
|
if (rc < 0)
|
|
return dev_err_probe(&pdev->dev, rc, "Could not read ngpios property\n");
|
|
|
|
rc = device_property_read_u32(&pdev->dev, "nuvoton,output-ngpios",
|
|
&nout_gpios);
|
|
if (rc < 0)
|
|
return dev_err_probe(&pdev->dev, rc, "Could not read ngpios property\n");
|
|
|
|
gpio->nin_sgpio = nin_gpios;
|
|
gpio->nout_sgpio = nout_gpios;
|
|
if (gpio->nin_sgpio > MAX_NR_HW_SGPIO ||
|
|
gpio->nout_sgpio > MAX_NR_HW_SGPIO)
|
|
return dev_err_probe(&pdev->dev, -EINVAL, "Number of GPIOs exceeds the maximum of %d: input: %d output: %d\n", MAX_NR_HW_SGPIO, nin_gpios, nout_gpios);
|
|
|
|
gpio->pclk = devm_clk_get(&pdev->dev, NULL);
|
|
if (IS_ERR(gpio->pclk))
|
|
return dev_err_probe(&pdev->dev, PTR_ERR(gpio->pclk), "Could not get pclk\n");
|
|
|
|
rc = npcm_sgpio_setup_clk(gpio, clk_cfg);
|
|
if (rc < 0)
|
|
return dev_err_probe(&pdev->dev, rc, "Failed to setup clock\n");
|
|
|
|
raw_spin_lock_init(&gpio->lock);
|
|
gpio->chip.parent = &pdev->dev;
|
|
gpio->chip.ngpio = gpio->nin_sgpio + gpio->nout_sgpio;
|
|
gpio->chip.direction_input = npcm_sgpio_dir_in;
|
|
gpio->chip.direction_output = npcm_sgpio_dir_out;
|
|
gpio->chip.get_direction = npcm_sgpio_get_direction;
|
|
gpio->chip.get = npcm_sgpio_get;
|
|
gpio->chip.set = npcm_sgpio_set;
|
|
gpio->chip.label = dev_name(&pdev->dev);
|
|
gpio->chip.base = -1;
|
|
|
|
rc = npcm_sgpio_init_port(gpio);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
rc = npcm_sgpio_setup_irqs(gpio, pdev);
|
|
if (rc < 0)
|
|
return rc;
|
|
|
|
rc = devm_gpiochip_add_data(&pdev->dev, &gpio->chip, gpio);
|
|
if (rc)
|
|
return dev_err_probe(&pdev->dev, rc, "GPIO registering failed\n");
|
|
|
|
npcm_sgpio_setup_enable(gpio, true);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static unsigned int npcm750_SFT_CLK[NPCM_750_OPT] = {
|
|
1024, 32, 8, 4, 3, 2,
|
|
};
|
|
|
|
static unsigned int npcm750_CLK_SEL[NPCM_750_OPT] = {
|
|
0x00, 0x05, 0x07, 0x0C, 0x0D, 0x0E,
|
|
};
|
|
|
|
static unsigned int npcm845_SFT_CLK[NPCM_845_OPT] = {
|
|
1024, 32, 16, 8, 4,
|
|
};
|
|
|
|
static unsigned int npcm845_CLK_SEL[NPCM_845_OPT] = {
|
|
0x00, 0x05, 0x06, 0x07, 0x0C,
|
|
};
|
|
|
|
static struct npcm_clk_cfg npcm750_sgpio_pdata = {
|
|
.sft_clk = npcm750_SFT_CLK,
|
|
.clk_sel = npcm750_CLK_SEL,
|
|
.cfg_opt = NPCM_750_OPT,
|
|
};
|
|
|
|
static const struct npcm_clk_cfg npcm845_sgpio_pdata = {
|
|
.sft_clk = npcm845_SFT_CLK,
|
|
.clk_sel = npcm845_CLK_SEL,
|
|
.cfg_opt = NPCM_845_OPT,
|
|
};
|
|
|
|
static const struct of_device_id npcm_sgpio_of_table[] = {
|
|
{ .compatible = "nuvoton,npcm750-sgpio", .data = &npcm750_sgpio_pdata, },
|
|
{ .compatible = "nuvoton,npcm845-sgpio", .data = &npcm845_sgpio_pdata, },
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, npcm_sgpio_of_table);
|
|
|
|
static struct platform_driver npcm_sgpio_driver = {
|
|
.driver = {
|
|
.name = KBUILD_MODNAME,
|
|
.of_match_table = npcm_sgpio_of_table,
|
|
},
|
|
.probe = npcm_sgpio_probe,
|
|
};
|
|
module_platform_driver(npcm_sgpio_driver);
|
|
|
|
MODULE_AUTHOR("Jim Liu <jjliu0@nuvoton.com>");
|
|
MODULE_AUTHOR("Joseph Liu <kwliu@nuvoton.com>");
|
|
MODULE_DESCRIPTION("Nuvoton NPCM Serial GPIO Driver");
|
|
MODULE_LICENSE("GPL v2");
|