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![Peter Colberg](/assets/img/avatar_default.png)
Add PCI subdevice ID for the Intel D5005 Stratix 10 FPGA card as used with the Open FPGA Stack (OFS) FPGA Interface Manager (FIM). Unlike the Intel D5005 PAC FIM which exposed a separate PCI device ID, the OFS FIM reuses the same device ID for all DFL-based FPGA cards and differentiates on the subdevice ID. The subdevice ID values were chosen as the numeric part of the FPGA card names in hexadecimal. Signed-off-by: Peter Colberg <peter.colberg@intel.com> Reviewed-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> Acked-by: Xu Yilun <yilun.xu@intel.com> Link: https://lore.kernel.org/r/20240422230257.1959-1-peter.colberg@intel.com Signed-off-by: Xu Yilun <yilun.xu@linux.intel.com>
455 lines
12 KiB
C
455 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for FPGA Device Feature List (DFL) PCIe device
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*
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* Copyright (C) 2017-2018 Intel Corporation, Inc.
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*
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* Authors:
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* Zhang Yi <Yi.Z.Zhang@intel.com>
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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* Joseph Grecco <joe.grecco@intel.com>
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* Enno Luebbers <enno.luebbers@intel.com>
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* Tim Whisonant <tim.whisonant@intel.com>
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* Ananda Ravuri <ananda.ravuri@intel.com>
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* Henry Mitchel <henry.mitchel@intel.com>
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*/
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#include <linux/pci.h>
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#include <linux/dma-mapping.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/stddef.h>
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#include <linux/errno.h>
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#include "dfl.h"
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#define DRV_VERSION "0.8"
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#define DRV_NAME "dfl-pci"
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#define PCI_VSEC_ID_INTEL_DFLS 0x43
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#define PCI_VNDR_DFLS_CNT 0x8
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#define PCI_VNDR_DFLS_RES 0xc
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#define PCI_VNDR_DFLS_RES_BAR_MASK GENMASK(2, 0)
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#define PCI_VNDR_DFLS_RES_OFF_MASK GENMASK(31, 3)
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struct cci_drvdata {
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struct dfl_fpga_cdev *cdev; /* container device */
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};
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static void __iomem *cci_pci_ioremap_bar0(struct pci_dev *pcidev)
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{
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if (pcim_iomap_regions(pcidev, BIT(0), DRV_NAME))
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return NULL;
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return pcim_iomap_table(pcidev)[0];
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}
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static int cci_pci_alloc_irq(struct pci_dev *pcidev)
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{
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int ret, nvec = pci_msix_vec_count(pcidev);
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if (nvec <= 0) {
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dev_dbg(&pcidev->dev, "fpga interrupt not supported\n");
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return 0;
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}
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ret = pci_alloc_irq_vectors(pcidev, nvec, nvec, PCI_IRQ_MSIX);
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if (ret < 0)
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return ret;
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return nvec;
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}
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static void cci_pci_free_irq(struct pci_dev *pcidev)
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{
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pci_free_irq_vectors(pcidev);
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}
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/* PCI Device ID */
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#define PCIE_DEVICE_ID_PF_INT_5_X 0xBCBD
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#define PCIE_DEVICE_ID_PF_INT_6_X 0xBCC0
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#define PCIE_DEVICE_ID_PF_DSC_1_X 0x09C4
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#define PCIE_DEVICE_ID_INTEL_PAC_N3000 0x0B30
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#define PCIE_DEVICE_ID_INTEL_PAC_D5005 0x0B2B
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#define PCIE_DEVICE_ID_SILICOM_PAC_N5010 0x1000
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#define PCIE_DEVICE_ID_SILICOM_PAC_N5011 0x1001
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#define PCIE_DEVICE_ID_INTEL_DFL 0xbcce
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/* PCI Subdevice ID for PCIE_DEVICE_ID_INTEL_DFL */
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#define PCIE_SUBDEVICE_ID_INTEL_D5005 0x138d
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#define PCIE_SUBDEVICE_ID_INTEL_N6000 0x1770
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#define PCIE_SUBDEVICE_ID_INTEL_N6001 0x1771
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#define PCIE_SUBDEVICE_ID_INTEL_C6100 0x17d4
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/* VF Device */
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#define PCIE_DEVICE_ID_VF_INT_5_X 0xBCBF
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#define PCIE_DEVICE_ID_VF_INT_6_X 0xBCC1
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#define PCIE_DEVICE_ID_VF_DSC_1_X 0x09C5
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#define PCIE_DEVICE_ID_INTEL_PAC_D5005_VF 0x0B2C
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#define PCIE_DEVICE_ID_INTEL_DFL_VF 0xbccf
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static struct pci_device_id cci_pcie_id_tbl[] = {
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_5_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_5_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_INT_6_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_INT_6_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_PF_DSC_1_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_VF_DSC_1_X),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_N3000),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005),},
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{PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_PAC_D5005_VF),},
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{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5010),},
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{PCI_DEVICE(PCI_VENDOR_ID_SILICOM_DENMARK, PCIE_DEVICE_ID_SILICOM_PAC_N5011),},
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{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
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PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_D5005),},
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{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
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PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6000),},
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{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF,
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PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6000),},
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{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
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PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6001),},
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{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF,
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PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_N6001),},
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{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL,
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PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_C6100),},
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{PCI_DEVICE_SUB(PCI_VENDOR_ID_INTEL, PCIE_DEVICE_ID_INTEL_DFL_VF,
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PCI_VENDOR_ID_INTEL, PCIE_SUBDEVICE_ID_INTEL_C6100),},
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{0,}
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};
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MODULE_DEVICE_TABLE(pci, cci_pcie_id_tbl);
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static int cci_init_drvdata(struct pci_dev *pcidev)
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{
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struct cci_drvdata *drvdata;
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drvdata = devm_kzalloc(&pcidev->dev, sizeof(*drvdata), GFP_KERNEL);
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if (!drvdata)
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return -ENOMEM;
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pci_set_drvdata(pcidev, drvdata);
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return 0;
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}
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static void cci_remove_feature_devs(struct pci_dev *pcidev)
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{
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struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
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/* remove all children feature devices */
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dfl_fpga_feature_devs_remove(drvdata->cdev);
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cci_pci_free_irq(pcidev);
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}
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static int *cci_pci_create_irq_table(struct pci_dev *pcidev, unsigned int nvec)
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{
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unsigned int i;
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int *table;
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table = kcalloc(nvec, sizeof(int), GFP_KERNEL);
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if (!table)
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return table;
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for (i = 0; i < nvec; i++)
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table[i] = pci_irq_vector(pcidev, i);
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return table;
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}
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static int find_dfls_by_vsec(struct pci_dev *pcidev, struct dfl_fpga_enum_info *info)
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{
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u32 bir, offset, dfl_cnt, dfl_res;
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int dfl_res_off, i, bars, voff;
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resource_size_t start, len;
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voff = pci_find_vsec_capability(pcidev, PCI_VENDOR_ID_INTEL,
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PCI_VSEC_ID_INTEL_DFLS);
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if (!voff) {
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dev_dbg(&pcidev->dev, "%s no DFL VSEC found\n", __func__);
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return -ENODEV;
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}
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dfl_cnt = 0;
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pci_read_config_dword(pcidev, voff + PCI_VNDR_DFLS_CNT, &dfl_cnt);
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if (dfl_cnt > PCI_STD_NUM_BARS) {
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dev_err(&pcidev->dev, "%s too many DFLs %d > %d\n",
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__func__, dfl_cnt, PCI_STD_NUM_BARS);
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return -EINVAL;
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}
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dfl_res_off = voff + PCI_VNDR_DFLS_RES;
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if (dfl_res_off + (dfl_cnt * sizeof(u32)) > PCI_CFG_SPACE_EXP_SIZE) {
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dev_err(&pcidev->dev, "%s DFL VSEC too big for PCIe config space\n",
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__func__);
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return -EINVAL;
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}
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for (i = 0, bars = 0; i < dfl_cnt; i++, dfl_res_off += sizeof(u32)) {
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dfl_res = GENMASK(31, 0);
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pci_read_config_dword(pcidev, dfl_res_off, &dfl_res);
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bir = dfl_res & PCI_VNDR_DFLS_RES_BAR_MASK;
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if (bir >= PCI_STD_NUM_BARS) {
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dev_err(&pcidev->dev, "%s bad bir number %d\n",
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__func__, bir);
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return -EINVAL;
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}
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if (bars & BIT(bir)) {
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dev_err(&pcidev->dev, "%s DFL for BAR %d already specified\n",
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__func__, bir);
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return -EINVAL;
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}
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bars |= BIT(bir);
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len = pci_resource_len(pcidev, bir);
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offset = dfl_res & PCI_VNDR_DFLS_RES_OFF_MASK;
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if (offset >= len) {
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dev_err(&pcidev->dev, "%s bad offset %u >= %pa\n",
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__func__, offset, &len);
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return -EINVAL;
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}
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dev_dbg(&pcidev->dev, "%s BAR %d offset 0x%x\n", __func__, bir, offset);
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len -= offset;
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start = pci_resource_start(pcidev, bir) + offset;
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dfl_fpga_enum_info_add_dfl(info, start, len);
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}
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return 0;
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}
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/* default method of finding dfls starting at offset 0 of bar 0 */
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static int find_dfls_by_default(struct pci_dev *pcidev,
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struct dfl_fpga_enum_info *info)
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{
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int port_num, bar, i, ret = 0;
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resource_size_t start, len;
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void __iomem *base;
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u32 offset;
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u64 v;
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/* start to find Device Feature List from Bar 0 */
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base = cci_pci_ioremap_bar0(pcidev);
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if (!base)
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return -ENOMEM;
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/*
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* PF device has FME and Ports/AFUs, and VF device only has one
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* Port/AFU. Check them and add related "Device Feature List" info
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* for the next step enumeration.
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*/
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if (dfl_feature_is_fme(base)) {
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start = pci_resource_start(pcidev, 0);
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len = pci_resource_len(pcidev, 0);
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dfl_fpga_enum_info_add_dfl(info, start, len);
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/*
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* find more Device Feature Lists (e.g. Ports) per information
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* indicated by FME module.
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*/
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v = readq(base + FME_HDR_CAP);
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port_num = FIELD_GET(FME_CAP_NUM_PORTS, v);
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WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM);
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for (i = 0; i < port_num; i++) {
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v = readq(base + FME_HDR_PORT_OFST(i));
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/* skip ports which are not implemented. */
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if (!(v & FME_PORT_OFST_IMP))
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continue;
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/*
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* add Port's Device Feature List information for next
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* step enumeration.
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*/
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bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v);
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offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v);
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if (bar == FME_PORT_OFST_BAR_SKIP) {
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continue;
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} else if (bar >= PCI_STD_NUM_BARS) {
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dev_err(&pcidev->dev, "bad BAR %d for port %d\n",
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bar, i);
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ret = -EINVAL;
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break;
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}
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start = pci_resource_start(pcidev, bar) + offset;
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len = pci_resource_len(pcidev, bar) - offset;
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dfl_fpga_enum_info_add_dfl(info, start, len);
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}
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} else if (dfl_feature_is_port(base)) {
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start = pci_resource_start(pcidev, 0);
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len = pci_resource_len(pcidev, 0);
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dfl_fpga_enum_info_add_dfl(info, start, len);
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} else {
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ret = -ENODEV;
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}
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/* release I/O mappings for next step enumeration */
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pcim_iounmap_regions(pcidev, BIT(0));
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return ret;
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}
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/* enumerate feature devices under pci device */
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static int cci_enumerate_feature_devs(struct pci_dev *pcidev)
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{
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struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
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struct dfl_fpga_enum_info *info;
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struct dfl_fpga_cdev *cdev;
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int nvec, ret = 0;
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int *irq_table;
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/* allocate enumeration info via pci_dev */
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info = dfl_fpga_enum_info_alloc(&pcidev->dev);
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if (!info)
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return -ENOMEM;
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/* add irq info for enumeration if the device support irq */
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nvec = cci_pci_alloc_irq(pcidev);
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if (nvec < 0) {
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dev_err(&pcidev->dev, "Fail to alloc irq %d.\n", nvec);
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ret = nvec;
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goto enum_info_free_exit;
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} else if (nvec) {
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irq_table = cci_pci_create_irq_table(pcidev, nvec);
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if (!irq_table) {
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ret = -ENOMEM;
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goto irq_free_exit;
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}
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ret = dfl_fpga_enum_info_add_irq(info, nvec, irq_table);
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kfree(irq_table);
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if (ret)
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goto irq_free_exit;
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}
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ret = find_dfls_by_vsec(pcidev, info);
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if (ret == -ENODEV)
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ret = find_dfls_by_default(pcidev, info);
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if (ret)
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goto irq_free_exit;
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/* start enumeration with prepared enumeration information */
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cdev = dfl_fpga_feature_devs_enumerate(info);
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if (IS_ERR(cdev)) {
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dev_err(&pcidev->dev, "Enumeration failure\n");
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ret = PTR_ERR(cdev);
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goto irq_free_exit;
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}
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drvdata->cdev = cdev;
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irq_free_exit:
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if (ret)
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cci_pci_free_irq(pcidev);
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enum_info_free_exit:
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dfl_fpga_enum_info_free(info);
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return ret;
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}
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static
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int cci_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *pcidevid)
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{
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int ret;
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ret = pcim_enable_device(pcidev);
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if (ret < 0) {
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dev_err(&pcidev->dev, "Failed to enable device %d.\n", ret);
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return ret;
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}
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pci_set_master(pcidev);
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ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64));
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if (ret)
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ret = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32));
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if (ret) {
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dev_err(&pcidev->dev, "No suitable DMA support available.\n");
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return ret;
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}
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ret = cci_init_drvdata(pcidev);
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if (ret) {
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dev_err(&pcidev->dev, "Fail to init drvdata %d.\n", ret);
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return ret;
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}
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ret = cci_enumerate_feature_devs(pcidev);
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if (ret) {
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dev_err(&pcidev->dev, "enumeration failure %d.\n", ret);
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return ret;
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}
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return 0;
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}
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static int cci_pci_sriov_configure(struct pci_dev *pcidev, int num_vfs)
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{
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struct cci_drvdata *drvdata = pci_get_drvdata(pcidev);
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struct dfl_fpga_cdev *cdev = drvdata->cdev;
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if (!num_vfs) {
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/*
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* disable SRIOV and then put released ports back to default
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* PF access mode.
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*/
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pci_disable_sriov(pcidev);
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dfl_fpga_cdev_config_ports_pf(cdev);
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} else {
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int ret;
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/*
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* before enable SRIOV, put released ports into VF access mode
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* first of all.
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*/
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ret = dfl_fpga_cdev_config_ports_vf(cdev, num_vfs);
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if (ret)
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return ret;
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ret = pci_enable_sriov(pcidev, num_vfs);
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if (ret) {
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dfl_fpga_cdev_config_ports_pf(cdev);
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return ret;
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}
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}
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return num_vfs;
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}
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static void cci_pci_remove(struct pci_dev *pcidev)
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{
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if (dev_is_pf(&pcidev->dev))
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cci_pci_sriov_configure(pcidev, 0);
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cci_remove_feature_devs(pcidev);
|
|
}
|
|
|
|
static struct pci_driver cci_pci_driver = {
|
|
.name = DRV_NAME,
|
|
.id_table = cci_pcie_id_tbl,
|
|
.probe = cci_pci_probe,
|
|
.remove = cci_pci_remove,
|
|
.sriov_configure = cci_pci_sriov_configure,
|
|
};
|
|
|
|
module_pci_driver(cci_pci_driver);
|
|
|
|
MODULE_DESCRIPTION("FPGA DFL PCIe Device Driver");
|
|
MODULE_AUTHOR("Intel Corporation");
|
|
MODULE_LICENSE("GPL v2");
|