Lucas Stach f513991b69 clk: rockchip: rk3568: Add PLL rate for 724 MHz ... This rate allows to provide a low-jitter 72,4 MHz pixelclock for a custom eDP panel from the VPLL. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Link: https://lore.kernel.org/r/20240503153329.3906030-1-l.stach@pengutronix.de Signed-off-by: Heiko Stuebner <heiko@sntech.de>		2024-05-04 12:38:13 +02:00
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clk-cpu.c
clk-ddr.c
clk-half-divider.c
clk-inverter.c
clk-mmc-phase.c	clk: rockchip: Remove an unused field in struct rockchip_mmc_clock	2024-05-04 12:38:02 +02:00
clk-muxgrf.c
clk-pll.c	clk: rockchip: Fix memory leak in rockchip_clk_register_pll()	2022-11-23 14:51:30 +01:00
clk-px30.c
clk-rk3036.c
clk-rk3128.c	clk: rockchip: rk3128: Fix SCLK_SDMMC's clock name	2023-11-28 10:30:59 +01:00
clk-rk3188.c
clk-rk3228.c
clk-rk3288.c
clk-rk3308.c
clk-rk3328.c
clk-rk3368.c
clk-rk3399.c	clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parent	2024-02-27 23:45:53 +01:00
clk-rk3568.c	clk: rockchip: rk3568: Add PLL rate for 724 MHz	2024-05-04 12:38:13 +02:00
clk-rk3588.c	clk: rockchip: rk3588: use linked clock ID for GATE_LINK	2024-02-27 22:23:06 +01:00
clk-rv1108.c
clk-rv1126.c	Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and 'clk-rockchip' into clk-next	2023-08-30 14:38:19 -07:00
clk.c	clk: rockchip: rk3588: fix CLK_NR_CLKS usage	2024-02-27 17:04:58 +01:00
clk.h	clk: rockchip: rk3588: fix CLK_NR_CLKS usage	2024-02-27 17:04:58 +01:00
Kconfig	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
Makefile	clk: rockchip: add clock controller for the RK3588	2022-11-15 11:37:41 +01:00
rst-rk3588.c	clk: rockchip: rk3588: Add reset line for HDMI Receiver	2024-04-10 07:10:40 +02:00
softrst.c	clk: rockchip: add lookup table support	2022-11-14 15:35:07 +01:00