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11f9323a48
Commit 07e461cd7e
"of: Ensure unique names without sacrificing determinism"
caused a boot failure regression on the Integrator machines.
The problem is probably caused by fiddling too much with
the device tree population in the OF init function, such
as passing the SoC bus device as parent when populating
the device tree.
This patch fixes the problem by:
- Avoiding to explicitly look up the tree root
- Look up devices needed before device population from
the match only, passing NULL as root
- Passing NULL as root and parent when calling
of_platform_populate()
After this the Integrators boot again. Tested on
Integrator/AP and Integrator/CP.
Cc: Grant Likely <grant.likely@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
337 lines
8.4 KiB
C
337 lines
8.4 KiB
C
/*
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* linux/arch/arm/mach-integrator/integrator_cp.c
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*
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* Copyright (C) 2003 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*/
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/string.h>
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#include <linux/device.h>
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#include <linux/amba/bus.h>
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#include <linux/amba/kmi.h>
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#include <linux/amba/clcd.h>
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#include <linux/amba/mmci.h>
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#include <linux/io.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/gfp.h>
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#include <linux/mtd/physmap.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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#include <linux/sys_soc.h>
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#include <linux/sched_clock.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include <plat/clcd.h>
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#include "hardware.h"
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#include "cm.h"
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#include "common.h"
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/* Base address to the CP controller */
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static void __iomem *intcp_con_base;
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#define INTCP_PA_FLASH_BASE 0x24000000
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#define INTCP_PA_CLCD_BASE 0xc0000000
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#define INTCP_FLASHPROG 0x04
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#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
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#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
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/*
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* Logical Physical
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* f1000000 10000000 Core module registers
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* f1300000 13000000 Counter/Timer
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* f1400000 14000000 Interrupt controller
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* f1600000 16000000 UART 0
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* f1700000 17000000 UART 1
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* f1a00000 1a000000 Debug LEDs
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* fc900000 c9000000 GPIO
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* fca00000 ca000000 SIC
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*/
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static struct map_desc intcp_io_desc[] __initdata __maybe_unused = {
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{
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.virtual = IO_ADDRESS(INTEGRATOR_HDR_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_HDR_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CT_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CT_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_IC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_IC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_UART0_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_UART0_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_DBG_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_DBG_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CP_GPIO_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_GPIO_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}, {
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.virtual = IO_ADDRESS(INTEGRATOR_CP_SIC_BASE),
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.pfn = __phys_to_pfn(INTEGRATOR_CP_SIC_BASE),
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.length = SZ_4K,
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.type = MT_DEVICE
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}
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};
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static void __init intcp_map_io(void)
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{
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iotable_init(intcp_io_desc, ARRAY_SIZE(intcp_io_desc));
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}
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/*
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* Flash handling.
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*/
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static int intcp_flash_init(struct platform_device *dev)
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{
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u32 val;
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val = readl(intcp_con_base + INTCP_FLASHPROG);
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val |= CINTEGRATOR_FLASHPROG_FLWREN;
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writel(val, intcp_con_base + INTCP_FLASHPROG);
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return 0;
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}
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static void intcp_flash_exit(struct platform_device *dev)
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{
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u32 val;
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val = readl(intcp_con_base + INTCP_FLASHPROG);
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val &= ~(CINTEGRATOR_FLASHPROG_FLVPPEN|CINTEGRATOR_FLASHPROG_FLWREN);
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writel(val, intcp_con_base + INTCP_FLASHPROG);
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}
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static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
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{
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u32 val;
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val = readl(intcp_con_base + INTCP_FLASHPROG);
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if (on)
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val |= CINTEGRATOR_FLASHPROG_FLVPPEN;
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else
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val &= ~CINTEGRATOR_FLASHPROG_FLVPPEN;
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writel(val, intcp_con_base + INTCP_FLASHPROG);
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}
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static struct physmap_flash_data intcp_flash_data = {
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.width = 4,
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.init = intcp_flash_init,
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.exit = intcp_flash_exit,
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.set_vpp = intcp_flash_set_vpp,
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};
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/*
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* It seems that the card insertion interrupt remains active after
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* we've acknowledged it. We therefore ignore the interrupt, and
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* rely on reading it from the SIC. This also means that we must
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* clear the latched interrupt.
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*/
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static unsigned int mmc_status(struct device *dev)
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{
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unsigned int status = readl(__io_address(0xca000000 + 4));
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writel(8, intcp_con_base + 8);
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return status & 8;
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}
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static struct mmci_platform_data mmc_data = {
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.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
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.status = mmc_status,
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.gpio_wp = -1,
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.gpio_cd = -1,
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};
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/*
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* CLCD support
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*/
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/*
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* Ensure VGA is selected.
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*/
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static void cp_clcd_enable(struct clcd_fb *fb)
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{
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struct fb_var_screeninfo *var = &fb->fb.var;
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u32 val = CM_CTRL_STATIC1 | CM_CTRL_STATIC2
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| CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1;
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if (var->bits_per_pixel <= 8 ||
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(var->bits_per_pixel == 16 && var->green.length == 5))
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/* Pseudocolor, RGB555, BGR555 */
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val |= CM_CTRL_LCDMUXSEL_VGA555_TFT555;
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else if (fb->fb.var.bits_per_pixel <= 16)
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/* truecolor RGB565 */
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val |= CM_CTRL_LCDMUXSEL_VGA565_TFT555;
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else
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val = 0; /* no idea for this, don't trust the docs */
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cm_control(CM_CTRL_LCDMUXSEL_MASK|
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CM_CTRL_LCDEN0|
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CM_CTRL_LCDEN1|
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CM_CTRL_STATIC1|
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CM_CTRL_STATIC2|
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CM_CTRL_STATIC|
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CM_CTRL_n24BITEN, val);
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}
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static int cp_clcd_setup(struct clcd_fb *fb)
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{
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fb->panel = versatile_clcd_get_panel("VGA");
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if (!fb->panel)
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return -EINVAL;
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return versatile_clcd_setup_dma(fb, SZ_1M);
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}
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static struct clcd_board clcd_data = {
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.name = "Integrator/CP",
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.caps = CLCD_CAP_5551 | CLCD_CAP_RGB565 | CLCD_CAP_888,
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.check = clcdfb_check,
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.decode = clcdfb_decode,
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.enable = cp_clcd_enable,
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.setup = cp_clcd_setup,
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.mmap = versatile_clcd_mmap_dma,
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.remove = versatile_clcd_remove_dma,
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};
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#define REFCOUNTER (__io_address(INTEGRATOR_HDR_BASE) + 0x28)
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static u64 notrace intcp_read_sched_clock(void)
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{
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return readl(REFCOUNTER);
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}
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static void __init intcp_init_early(void)
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{
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sched_clock_register(intcp_read_sched_clock, 32, 24000000);
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}
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static const struct of_device_id fpga_irq_of_match[] __initconst = {
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{ .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, },
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{ /* Sentinel */ }
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};
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static void __init intcp_init_irq_of(void)
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{
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cm_init();
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of_irq_init(fpga_irq_of_match);
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}
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/*
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* For the Device Tree, add in the UART, MMC and CLCD specifics as AUXDATA
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* and enforce the bus names since these are used for clock lookups.
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*/
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static struct of_dev_auxdata intcp_auxdata_lookup[] __initdata = {
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_RTC_BASE,
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"rtc", NULL),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART0_BASE,
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"uart0", NULL),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_UART1_BASE,
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"uart1", NULL),
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OF_DEV_AUXDATA("arm,primecell", KMI0_BASE,
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"kmi0", NULL),
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OF_DEV_AUXDATA("arm,primecell", KMI1_BASE,
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"kmi1", NULL),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_MMC_BASE,
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"mmci", &mmc_data),
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OF_DEV_AUXDATA("arm,primecell", INTEGRATOR_CP_AACI_BASE,
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"aaci", &mmc_data),
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OF_DEV_AUXDATA("arm,primecell", INTCP_PA_CLCD_BASE,
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"clcd", &clcd_data),
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OF_DEV_AUXDATA("cfi-flash", INTCP_PA_FLASH_BASE,
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"physmap-flash", &intcp_flash_data),
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{ /* sentinel */ },
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};
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static const struct of_device_id intcp_syscon_match[] = {
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{ .compatible = "arm,integrator-cp-syscon"},
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{ },
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};
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static void __init intcp_init_of(void)
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{
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struct device_node *cpcon;
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struct device *parent;
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struct soc_device *soc_dev;
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struct soc_device_attribute *soc_dev_attr;
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u32 intcp_sc_id;
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cpcon = of_find_matching_node(NULL, intcp_syscon_match);
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if (!cpcon)
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return;
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intcp_con_base = of_iomap(cpcon, 0);
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if (!intcp_con_base)
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return;
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of_platform_populate(NULL, of_default_bus_match_table,
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intcp_auxdata_lookup, NULL);
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intcp_sc_id = readl(intcp_con_base);
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soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
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if (!soc_dev_attr)
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return;
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soc_dev_attr->soc_id = "XCV";
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soc_dev_attr->machine = "Integrator/CP";
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soc_dev_attr->family = "Integrator";
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soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%c",
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'A' + (intcp_sc_id & 0x0f));
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soc_dev = soc_device_register(soc_dev_attr);
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if (IS_ERR(soc_dev)) {
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kfree(soc_dev_attr->revision);
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kfree(soc_dev_attr);
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return;
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}
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parent = soc_device_to_device(soc_dev);
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integrator_init_sysfs(parent, intcp_sc_id);
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}
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static const char * intcp_dt_board_compat[] = {
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"arm,integrator-cp",
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NULL,
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};
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DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
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.reserve = integrator_reserve,
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.map_io = intcp_map_io,
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.init_early = intcp_init_early,
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.init_irq = intcp_init_irq_of,
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.handle_irq = fpga_handle_irq,
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.init_machine = intcp_init_of,
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.restart = integrator_restart,
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.dt_compat = intcp_dt_board_compat,
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MACHINE_END
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