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-----BEGIN PGP SIGNATURE----- iQJIBAABCgAyFiEEgMe7l+5h9hnxdsnuWYigwDrT+vwFAmGFXBkUHGJoZWxnYWFz QGdvb2dsZS5jb20ACgkQWYigwDrT+vx6Tg/7BsGWm8f+uw/mr9lLm47q2mc4XyoO 7bR9KDp5NM84W/8ZOU7dqqqsnY0ddrSOLBRyhJJYMW3SwJd1y1ajTBsL1Ujqv+eN z+JUFmhq4Laqm4k6Spc9CEJE+Ol5P6gGUtxLYo6PM2R0VxnSs/rDxctT5i7YOpCi COJ+NVT/mc/by2loz1kLTSR9GgtBBgd+Y8UA33GFbHKssROw02L0OI3wffp81Oba EhMGPoD+0FndAniDw+vaOSoO+YaBuTfbM92T/O00mND69Fj1PWgmNWZz7gAVgsXb 3RrNENUFxgw6CDt7LZWB8OyT04iXe0R2kJs+PA9gigFCGbypwbd/Nbz5M7e9HUTR ray+1EpZib6+nIksQBL2mX8nmtyHMcLiM57TOEhq0+ECDO640MiRm8t0FIG/1E8v 3ZYd9w20o/NxlFNXHxxpZ3D/osGH5ocyF5c5m1rfB4RGRwztZGL172LWCB0Ezz9r eHB8sWxylxuhrH+hp2BzQjyddg7rbF+RA4AVfcQSxUpyV01hoRocKqknoDATVeLH 664nJIINFxKJFwfuL3E6OhrInNe1LnAhCZsHHqbS+NNQFgvPRznbixBeLkI9dMf5 Yf6vpsWO7ur8lHHbRndZubVu8nxklXTU7B/w+C11sq6k9LLRJSHzanr3Fn9WA80x sznCxwUvbTCu1r0= =nsMh -----END PGP SIGNATURE----- Merge tag 'pci-v5.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Conserve IRQs by setting up portdrv IRQs only when there are users (Jan Kiszka) - Rework and simplify _OSC negotiation for control of PCIe features (Joerg Roedel) - Remove struct pci_dev.driver pointer since it's redundant with the struct device.driver pointer (Uwe Kleine-König) Resource management: - Coalesce contiguous host bridge apertures from _CRS to accommodate BARs that cover more than one aperture (Kai-Heng Feng) Sysfs: - Check CAP_SYS_ADMIN before parsing user input (Krzysztof Wilczyński) - Return -EINVAL consistently from "store" functions (Krzysztof Wilczyński) - Use sysfs_emit() in endpoint "show" functions to avoid buffer overruns (Kunihiko Hayashi) PCIe native device hotplug: - Ignore Link Down/Up caused by resets during error recovery so endpoint drivers can remain bound to the device (Lukas Wunner) Virtualization: - Avoid bus resets on Atheros QCA6174, where they hang the device (Ingmar Klein) - Work around Pericom PI7C9X2G switch packet drop erratum by using store and forward mode instead of cut-through (Nathan Rossi) - Avoid trying to enable AtomicOps on VFs; the PF setting applies to all VFs (Selvin Xavier) MSI: - Document that /sys/bus/pci/devices/.../irq contains the legacy INTx interrupt or the IRQ of the first MSI (not MSI-X) vector (Barry Song) VPD: - Add pci_read_vpd_any() and pci_write_vpd_any() to access anywhere in the possible VPD space; use these to simplify the cxgb3 driver (Heiner Kallweit) Peer-to-peer DMA: - Add (not subtract) the bus offset when calculating DMA address (Wang Lu) ASPM: - Re-enable LTR at Downstream Ports so they don't report Unsupported Requests when reset or hot-added devices send LTR messages (Mingchuang Qiao) Apple PCIe controller driver: - Add driver for Apple M1 PCIe controller (Alyssa Rosenzweig, Marc Zyngier) Cadence PCIe controller driver: - Return success when probe succeeds instead of falling into error path (Li Chen) HiSilicon Kirin PCIe controller driver: - Reorganize PHY logic and add support for external PHY drivers (Mauro Carvalho Chehab) - Support PERST# GPIOs for HiKey970 external PEX 8606 bridge (Mauro Carvalho Chehab) - Add Kirin 970 support (Mauro Carvalho Chehab) - Make driver removable (Mauro Carvalho Chehab) Intel VMD host bridge driver: - If IOMMU supports interrupt remapping, leave VMD MSI-X remapping enabled (Adrian Huang) - Number each controller so we can tell them apart in /proc/interrupts (Chunguang Xu) - Avoid building on UML because VMD depends on x86 bare metal APIs (Johannes Berg) Marvell Aardvark PCIe controller driver: - Define macros for PCI_EXP_DEVCTL_PAYLOAD_* (Pali Rohár) - Set Max Payload Size to 512 bytes per Marvell spec (Pali Rohár) - Downgrade PIO Response Status messages to debug level (Marek Behún) - Preserve CRS SV (Config Request Retry Software Visibility) bit in emulated Root Control register (Pali Rohár) - Fix issue in configuring reference clock (Pali Rohár) - Don't clear status bits for masked interrupts (Pali Rohár) - Don't mask unused interrupts (Pali Rohár) - Avoid code repetition in advk_pcie_rd_conf() (Marek Behún) - Retry config accesses on CRS response (Pali Rohár) - Simplify emulated Root Capabilities initialization (Pali Rohár) - Fix several link training issues (Pali Rohár) - Fix link-up checking via LTSSM (Pali Rohár) - Fix reporting of Data Link Layer Link Active (Pali Rohár) - Fix emulation of W1C bits (Marek Behún) - Fix MSI domain .alloc() method to return zero on success (Marek Behún) - Read entire 16-bit MSI vector in MSI handler, not just low 8 bits (Marek Behún) - Clear Root Port I/O Space, Memory Space, and Bus Master Enable bits at startup; PCI core will set those as necessary (Pali Rohár) - When operating as a Root Port, set class code to "PCI Bridge" instead of the default "Mass Storage Controller" (Pali Rohár) - Add emulation for PCI_BRIDGE_CTL_BUS_RESET since aardvark doesn't implement this per spec (Pali Rohár) - Add emulation of option ROM BAR since aardvark doesn't implement this per spec (Pali Rohár) MediaTek MT7621 PCIe controller driver: - Add MediaTek MT7621 PCIe host controller driver and DT binding (Sergio Paracuellos) Qualcomm PCIe controller driver: - Add SC8180x compatible string (Bjorn Andersson) - Add endpoint controller driver and DT binding (Manivannan Sadhasivam) - Restructure to use of_device_get_match_data() (Prasad Malisetty) - Add SC7280-specific pcie_1_pipe_clk_src handling (Prasad Malisetty) Renesas R-Car PCIe controller driver: - Remove unnecessary includes (Geert Uytterhoeven) Rockchip DesignWare PCIe controller driver: - Add DT binding (Simon Xue) Socionext UniPhier Pro5 controller driver: - Serialize INTx masking/unmasking (Kunihiko Hayashi) Synopsys DesignWare PCIe controller driver: - Run dwc .host_init() method before registering MSI interrupt handler so we can deal with pending interrupts left by bootloader (Bjorn Andersson) - Clean up Kconfig dependencies (Andy Shevchenko) - Export symbols to allow more modular drivers (Luca Ceresoli) TI DRA7xx PCIe controller driver: - Allow host and endpoint drivers to be modules (Luca Ceresoli) - Enable external clock if present (Luca Ceresoli) TI J721E PCIe driver: - Disable PHY when probe fails after initializing it (Christophe JAILLET) MicroSemi Switchtec management driver: - Return error to application when command execution fails because an out-of-band reset has cleared the device BARs, Memory Space Enable, etc (Kelvin Cao) - Fix MRPC error status handling issue (Kelvin Cao) - Mask out other bits when reading of management VEP instance ID (Kelvin Cao) - Return EOPNOTSUPP instead of ENOTSUPP from sysfs show functions (Kelvin Cao) - Add check of event support (Logan Gunthorpe) Miscellaneous: - Remove unused pci_pool wrappers, which have been replaced by dma_pool (Cai Huoqing) - Use 'unsigned int' instead of bare 'unsigned' (Krzysztof Wilczyński) - Use kstrtobool() directly, sans strtobool() wrapper (Krzysztof Wilczyński) - Fix some sscanf(), sprintf() format mismatches (Krzysztof Wilczyński) - Update PCI subsystem information in MAINTAINERS (Krzysztof Wilczyński) - Correct some misspellings (Krzysztof Wilczyński)" * tag 'pci-v5.16-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (137 commits) PCI: Add ACS quirk for Pericom PI7C9X2G switches PCI: apple: Configure RID to SID mapper on device addition iommu/dart: Exclude MSI doorbell from PCIe device IOVA range PCI: apple: Implement MSI support PCI: apple: Add INTx and per-port interrupt support PCI: kirin: Allow removing the driver PCI: kirin: De-init the dwc driver PCI: kirin: Disable clkreq during poweroff sequence PCI: kirin: Move the power-off code to a common routine PCI: kirin: Add power_off support for Kirin 960 PHY PCI: kirin: Allow building it as a module PCI: kirin: Add MODULE_* macros PCI: kirin: Add Kirin 970 compatible PCI: kirin: Support PERST# GPIOs for HiKey970 external PEX 8606 bridge PCI: apple: Set up reference clocks when probing PCI: apple: Add initial hardware bring-up PCI: of: Allow matching of an interrupt-map local to a PCI device of/irq: Allow matching of an interrupt-map local to an interrupt controller irqdomain: Make of_phandle_args_to_fwspec() generally available PCI: Do not enable AtomicOps on VFs ...
265 lines
9.6 KiB
C
265 lines
9.6 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2014 - 2020 Intel Corporation */
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#ifndef ADF_DRV_H
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#define ADF_DRV_H
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#include <linux/list.h>
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#include <linux/pci.h>
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#include "adf_accel_devices.h"
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#include "icp_qat_fw_loader_handle.h"
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#include "icp_qat_hal.h"
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#define ADF_MAJOR_VERSION 0
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#define ADF_MINOR_VERSION 6
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#define ADF_BUILD_VERSION 0
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#define ADF_DRV_VERSION __stringify(ADF_MAJOR_VERSION) "." \
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__stringify(ADF_MINOR_VERSION) "." \
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__stringify(ADF_BUILD_VERSION)
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#define ADF_STATUS_RESTARTING 0
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#define ADF_STATUS_STARTING 1
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#define ADF_STATUS_CONFIGURED 2
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#define ADF_STATUS_STARTED 3
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#define ADF_STATUS_AE_INITIALISED 4
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#define ADF_STATUS_AE_UCODE_LOADED 5
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#define ADF_STATUS_AE_STARTED 6
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#define ADF_STATUS_PF_RUNNING 7
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#define ADF_STATUS_IRQ_ALLOCATED 8
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enum adf_dev_reset_mode {
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ADF_DEV_RESET_ASYNC = 0,
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ADF_DEV_RESET_SYNC
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};
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enum adf_event {
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ADF_EVENT_INIT = 0,
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ADF_EVENT_START,
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ADF_EVENT_STOP,
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ADF_EVENT_SHUTDOWN,
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ADF_EVENT_RESTARTING,
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ADF_EVENT_RESTARTED,
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};
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struct service_hndl {
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int (*event_hld)(struct adf_accel_dev *accel_dev,
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enum adf_event event);
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unsigned long init_status[ADF_DEVS_ARRAY_SIZE];
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unsigned long start_status[ADF_DEVS_ARRAY_SIZE];
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char *name;
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struct list_head list;
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};
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static inline int get_current_node(void)
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{
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return topology_physical_package_id(raw_smp_processor_id());
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}
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int adf_service_register(struct service_hndl *service);
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int adf_service_unregister(struct service_hndl *service);
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int adf_dev_init(struct adf_accel_dev *accel_dev);
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int adf_dev_start(struct adf_accel_dev *accel_dev);
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void adf_dev_stop(struct adf_accel_dev *accel_dev);
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void adf_dev_shutdown(struct adf_accel_dev *accel_dev);
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void adf_pf2vf_notify_restarting(struct adf_accel_dev *accel_dev);
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int adf_enable_vf2pf_comms(struct adf_accel_dev *accel_dev);
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void adf_vf2pf_req_hndl(struct adf_accel_vf_info *vf_info);
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void adf_devmgr_update_class_index(struct adf_hw_device_data *hw_data);
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void adf_clean_vf_map(bool);
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int adf_ctl_dev_register(void);
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void adf_ctl_dev_unregister(void);
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int adf_processes_dev_register(void);
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void adf_processes_dev_unregister(void);
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int adf_devmgr_add_dev(struct adf_accel_dev *accel_dev,
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struct adf_accel_dev *pf);
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void adf_devmgr_rm_dev(struct adf_accel_dev *accel_dev,
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struct adf_accel_dev *pf);
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struct list_head *adf_devmgr_get_head(void);
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struct adf_accel_dev *adf_devmgr_get_dev_by_id(u32 id);
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struct adf_accel_dev *adf_devmgr_get_first(void);
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struct adf_accel_dev *adf_devmgr_pci_to_accel_dev(struct pci_dev *pci_dev);
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int adf_devmgr_verify_id(u32 id);
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void adf_devmgr_get_num_dev(u32 *num);
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int adf_devmgr_in_reset(struct adf_accel_dev *accel_dev);
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int adf_dev_started(struct adf_accel_dev *accel_dev);
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int adf_dev_restarting_notify(struct adf_accel_dev *accel_dev);
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int adf_dev_restarted_notify(struct adf_accel_dev *accel_dev);
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int adf_ae_init(struct adf_accel_dev *accel_dev);
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int adf_ae_shutdown(struct adf_accel_dev *accel_dev);
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int adf_ae_fw_load(struct adf_accel_dev *accel_dev);
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void adf_ae_fw_release(struct adf_accel_dev *accel_dev);
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int adf_ae_start(struct adf_accel_dev *accel_dev);
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int adf_ae_stop(struct adf_accel_dev *accel_dev);
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extern const struct pci_error_handlers adf_err_handler;
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void adf_enable_aer(struct adf_accel_dev *accel_dev);
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void adf_disable_aer(struct adf_accel_dev *accel_dev);
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void adf_reset_sbr(struct adf_accel_dev *accel_dev);
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void adf_reset_flr(struct adf_accel_dev *accel_dev);
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void adf_dev_restore(struct adf_accel_dev *accel_dev);
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int adf_init_aer(void);
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void adf_exit_aer(void);
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int adf_init_admin_comms(struct adf_accel_dev *accel_dev);
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void adf_exit_admin_comms(struct adf_accel_dev *accel_dev);
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int adf_send_admin_init(struct adf_accel_dev *accel_dev);
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int adf_init_arb(struct adf_accel_dev *accel_dev);
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void adf_exit_arb(struct adf_accel_dev *accel_dev);
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void adf_update_ring_arb(struct adf_etr_ring_data *ring);
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int adf_dev_get(struct adf_accel_dev *accel_dev);
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void adf_dev_put(struct adf_accel_dev *accel_dev);
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int adf_dev_in_use(struct adf_accel_dev *accel_dev);
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int adf_init_etr_data(struct adf_accel_dev *accel_dev);
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void adf_cleanup_etr_data(struct adf_accel_dev *accel_dev);
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int qat_crypto_register(void);
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int qat_crypto_unregister(void);
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int qat_crypto_dev_config(struct adf_accel_dev *accel_dev);
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struct qat_crypto_instance *qat_crypto_get_instance_node(int node);
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void qat_crypto_put_instance(struct qat_crypto_instance *inst);
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void qat_alg_callback(void *resp);
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void qat_alg_asym_callback(void *resp);
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int qat_algs_register(void);
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void qat_algs_unregister(void);
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int qat_asym_algs_register(void);
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void qat_asym_algs_unregister(void);
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int adf_isr_resource_alloc(struct adf_accel_dev *accel_dev);
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void adf_isr_resource_free(struct adf_accel_dev *accel_dev);
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int adf_vf_isr_resource_alloc(struct adf_accel_dev *accel_dev);
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void adf_vf_isr_resource_free(struct adf_accel_dev *accel_dev);
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int qat_hal_init(struct adf_accel_dev *accel_dev);
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void qat_hal_deinit(struct icp_qat_fw_loader_handle *handle);
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int qat_hal_start(struct icp_qat_fw_loader_handle *handle);
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void qat_hal_stop(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
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unsigned int ctx_mask);
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void qat_hal_reset(struct icp_qat_fw_loader_handle *handle);
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int qat_hal_clr_reset(struct icp_qat_fw_loader_handle *handle);
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void qat_hal_set_live_ctx(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned int ctx_mask);
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int qat_hal_check_ae_active(struct icp_qat_fw_loader_handle *handle,
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unsigned int ae);
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int qat_hal_set_ae_lm_mode(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, enum icp_qat_uof_regtype lm_type,
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unsigned char mode);
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int qat_hal_set_ae_ctx_mode(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned char mode);
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int qat_hal_set_ae_nn_mode(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned char mode);
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void qat_hal_set_pc(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned int ctx_mask, unsigned int upc);
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void qat_hal_wr_uwords(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned int uaddr,
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unsigned int words_num, u64 *uword);
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void qat_hal_wr_umem(struct icp_qat_fw_loader_handle *handle, unsigned char ae,
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unsigned int uword_addr, unsigned int words_num,
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unsigned int *data);
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int qat_hal_get_ins_num(void);
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int qat_hal_batch_wr_lm(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae,
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struct icp_qat_uof_batch_init *lm_init_header);
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int qat_hal_init_gpr(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned long ctx_mask,
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enum icp_qat_uof_regtype reg_type,
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unsigned short reg_num, unsigned int regdata);
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int qat_hal_init_wr_xfer(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned long ctx_mask,
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enum icp_qat_uof_regtype reg_type,
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unsigned short reg_num, unsigned int regdata);
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int qat_hal_init_rd_xfer(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned long ctx_mask,
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enum icp_qat_uof_regtype reg_type,
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unsigned short reg_num, unsigned int regdata);
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int qat_hal_init_nn(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned long ctx_mask,
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unsigned short reg_num, unsigned int regdata);
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int qat_hal_wr_lm(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned short lm_addr, unsigned int value);
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void qat_hal_set_ae_tindex_mode(struct icp_qat_fw_loader_handle *handle,
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unsigned char ae, unsigned char mode);
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int qat_uclo_wr_all_uimage(struct icp_qat_fw_loader_handle *handle);
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void qat_uclo_del_obj(struct icp_qat_fw_loader_handle *handle);
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int qat_uclo_wr_mimage(struct icp_qat_fw_loader_handle *handle, void *addr_ptr,
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int mem_size);
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int qat_uclo_map_obj(struct icp_qat_fw_loader_handle *handle,
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void *addr_ptr, u32 mem_size, char *obj_name);
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int qat_uclo_set_cfg_ae_mask(struct icp_qat_fw_loader_handle *handle,
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unsigned int cfg_ae_mask);
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#if defined(CONFIG_PCI_IOV)
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int adf_sriov_configure(struct pci_dev *pdev, int numvfs);
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void adf_disable_sriov(struct adf_accel_dev *accel_dev);
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void adf_disable_vf2pf_interrupts(struct adf_accel_dev *accel_dev,
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u32 vf_mask);
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void adf_disable_vf2pf_interrupts_irq(struct adf_accel_dev *accel_dev,
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u32 vf_mask);
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void adf_enable_vf2pf_interrupts(struct adf_accel_dev *accel_dev,
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u32 vf_mask);
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int adf_enable_pf2vf_comms(struct adf_accel_dev *accel_dev);
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void adf_enable_pf2vf_interrupts(struct adf_accel_dev *accel_dev);
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void adf_disable_pf2vf_interrupts(struct adf_accel_dev *accel_dev);
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void adf_schedule_vf2pf_handler(struct adf_accel_vf_info *vf_info);
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int adf_send_vf2pf_msg(struct adf_accel_dev *accel_dev, u32 msg);
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int adf_vf2pf_notify_init(struct adf_accel_dev *accel_dev);
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void adf_vf2pf_notify_shutdown(struct adf_accel_dev *accel_dev);
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int adf_init_pf_wq(void);
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void adf_exit_pf_wq(void);
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int adf_init_vf_wq(void);
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void adf_exit_vf_wq(void);
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void adf_flush_vf_wq(struct adf_accel_dev *accel_dev);
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#else
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#define adf_sriov_configure NULL
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static inline int adf_enable_pf2vf_comms(struct adf_accel_dev *accel_dev)
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{
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return 0;
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}
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static inline void adf_disable_sriov(struct adf_accel_dev *accel_dev)
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{
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}
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static inline void adf_enable_pf2vf_interrupts(struct adf_accel_dev *accel_dev)
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{
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}
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static inline void adf_disable_pf2vf_interrupts(struct adf_accel_dev *accel_dev)
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{
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}
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static inline int adf_vf2pf_notify_init(struct adf_accel_dev *accel_dev)
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{
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return 0;
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|
}
|
|
|
|
static inline void adf_vf2pf_notify_shutdown(struct adf_accel_dev *accel_dev)
|
|
{
|
|
}
|
|
|
|
static inline int adf_init_pf_wq(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void adf_exit_pf_wq(void)
|
|
{
|
|
}
|
|
|
|
static inline int adf_init_vf_wq(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static inline void adf_exit_vf_wq(void)
|
|
{
|
|
}
|
|
|
|
static inline void adf_flush_vf_wq(struct adf_accel_dev *accel_dev)
|
|
{
|
|
}
|
|
|
|
#endif
|
|
#endif
|