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https://github.com/torvalds/linux
synced 2024-09-20 02:57:25 +00:00
f7f847b015
This reverts commit e66485d747, since
Rafael Wysocki noticed that the change only works for his in -mm, not in
mainline (and that both "noapictimer" _and_ "apicmaintimer" are broken
on his hardware, but that's apparently not a regression, just a symptom
of the same issue that causes the automatic apic timer disable to not
work).
It turns out that it really doesn't work correctly on x86-64, since
x86-64 doesn't use the generic clock events for timers yet.
Thanks to Rafal for testing, and here's the ugly details on x86-64 as
per Thomas:
"I just looked into the code and the logic vs. noapictimer on SMP is
completely broken.
On i386 the noapictimer option not only disables the local APIC
timer, it also registers the CPUs for broadcasting via IPI on SMP
systems.
The x86-64 code uses the broadcast only when the local apic timer is
active, i.e. "noapictimer" is not on the command line. This defeats
the whole purpose of "noapictimer". It should be there to make boxen
work, where the local APIC timer actually has a hardware problem,
e.g. the nx6325.
The current implementation of x86_64 only fixes the ACPI c-states
related problem where the APIC timer stops in C3(2), nothing else.
On nx6325 and other AMD X2 equipped systems which have the C1E
enabled we run into the following:
PIT keeps jiffies (and the system) running, but the local APIC timer
interrupts can get out of sync due to this C1E effect.
I don't think this is a critical problem, but it is wrong
nevertheless.
I think it's safe to revert the C1E patch and postpone the fix to the
clock events conversion."
On further reflection, Thomas noted:
"It's even worse than I thought on the first check:
"noapictimer" on the command line of an SMP box prevents _ONLY_ the
boot CPU apic timer from being used. But the secondary CPU is still
unconditionally setting up the APIC timer and uses the non
calibrated variable calibration_result, which is of course 0, to
setup the APIC timer. Wreckage guaranteed."
so we'll just have to wait for the x86 merge to hopefully fix this up
for x86-64.
Tested-and-requested-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
108 lines
2.7 KiB
C
108 lines
2.7 KiB
C
#ifndef __ASM_APIC_H
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#define __ASM_APIC_H
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#include <linux/pm.h>
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#include <linux/delay.h>
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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#include <asm/system.h>
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#define Dprintk(x...)
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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extern int apic_verbosity;
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extern int apic_runs_main_timer;
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extern int ioapic_force;
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extern int apic_mapped;
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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struct pt_regs;
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/*
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* Basic functions accessing APICs.
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*/
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static __inline void apic_write(unsigned long reg, unsigned int v)
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{
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*((volatile unsigned int *)(APIC_BASE+reg)) = v;
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}
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static __inline unsigned int apic_read(unsigned long reg)
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{
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return *((volatile unsigned int *)(APIC_BASE+reg));
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}
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extern void apic_wait_icr_idle(void);
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extern unsigned int safe_apic_wait_icr_idle(void);
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction:
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* - a single rmw on Pentium/82489DX
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* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write(APIC_EOI, 0);
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}
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extern int get_maxlvt (void);
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extern void clear_local_APIC (void);
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extern void connect_bsp_APIC (void);
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extern void disconnect_bsp_APIC (int virt_wire_setup);
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extern void disable_local_APIC (void);
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extern int verify_local_APIC (void);
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extern void cache_APIC_registers (void);
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extern void sync_Arb_IDs (void);
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extern void init_bsp_APIC (void);
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extern void setup_local_APIC (void);
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extern void init_apic_mappings (void);
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extern void smp_local_timer_interrupt (void);
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extern void setup_boot_APIC_clock (void);
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extern void setup_secondary_APIC_clock (void);
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extern int APIC_init_uniprocessor (void);
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extern void disable_APIC_timer(void);
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extern void enable_APIC_timer(void);
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extern void setup_apic_routing(void);
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extern void setup_APIC_extended_lvt(unsigned char lvt_off, unsigned char vector,
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unsigned char msg_type, unsigned char mask);
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extern int apic_is_clustered_box(void);
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#define K8_APIC_EXT_LVT_BASE 0x500
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#define K8_APIC_EXT_INT_MSG_FIX 0x0
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#define K8_APIC_EXT_INT_MSG_SMI 0x2
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#define K8_APIC_EXT_INT_MSG_NMI 0x4
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#define K8_APIC_EXT_INT_MSG_EXT 0x7
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#define K8_APIC_EXT_LVT_ENTRY_THRESHOLD 0
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void smp_send_timer_broadcast_ipi(void);
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void switch_APIC_timer_to_ipi(void *cpumask);
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void switch_ipi_to_APIC_timer(void *cpumask);
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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extern unsigned boot_cpu_id;
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extern int local_apic_timer_c2_ok;
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#endif /* __ASM_APIC_H */
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