Dave Jiang 1037b82fcc cxl: Store the access coordinates for the generic ports ... Each CXL host bridge is represented by an ACPI0016 device. A generic port device handle that is an ACPI device is represented by a string of ACPI0016 device HID and UID. Create a device handle from the ACPI device and retrieve the access coordinates from the stored memory targets. The access coordinates are stored under the cxl_dport that is associated with the CXL host bridge. The access coordinates struct is dynamically allocated under cxl_dport in order for code later on to detect whether the data exists or not. Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Link: https://lore.kernel.org/r/170319623196.2212653.17916695743464172534.stgit@djiang5-mobl3 Signed-off-by: Dan Williams <dan.j.williams@intel.com>		2023-12-22 15:31:52 -08:00
..
core	cxl: Calculate and store PCI link latency for the downstream ports	2023-12-22 14:53:49 -08:00
acpi.c	cxl: Store the access coordinates for the generic ports	2023-12-22 15:31:52 -08:00
cxl.h	cxl: Store the access coordinates for the generic ports	2023-12-22 15:31:52 -08:00
cxlmem.h
cxlpci.h	cxl: Calculate and store PCI link latency for the downstream ports	2023-12-22 14:53:49 -08:00
Kconfig
Makefile
mem.c
pci.c
pmem.c
pmu.h
port.c
security.c