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efc1bb8a6f
This patch adds core power management (suspend-to-RAM) support for DaVinci SoCs. The code depends on the the "deepsleep" feature to suspend the SoC and saves power by gating the input clock. The wakeup can be based on an external event as supported by the SoC. Assembly code (in sleep.S) is added to aid gating DDR2 clocks. Code doing this work should not be accessing DDR2. The assembly code is relocated to SRAM by the code in pm.c The support has been validated on DA850/OMAP-L138 only though the code is (hopefully) generic enough that other SoCs supporting deepsleep feature simply requires SoC specific code to start using this driver. Note that all the device drivers don't support suspend/resume still and are being worked on. Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Kevin Hilman <khilman@deeprootsystems.com>
71 lines
2 KiB
C
71 lines
2 KiB
C
/*
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* DaVinci memory space definitions
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*
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* Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
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*
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* 2007 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#ifndef __ASM_ARCH_MEMORY_H
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#define __ASM_ARCH_MEMORY_H
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/**************************************************************************
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* Included Files
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**************************************************************************/
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#include <asm/page.h>
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#include <asm/sizes.h>
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/**************************************************************************
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* Definitions
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**************************************************************************/
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#define DAVINCI_DDR_BASE 0x80000000
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#define DA8XX_DDR_BASE 0xc0000000
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#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
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#error Cannot enable DaVinci and DA8XX platforms concurrently
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#elif defined(CONFIG_ARCH_DAVINCI_DA8XX)
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#define PHYS_OFFSET DA8XX_DDR_BASE
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#else
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#define PHYS_OFFSET DAVINCI_DDR_BASE
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#endif
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#define DDR2_SDRCR_OFFSET 0xc
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#define DDR2_SRPD_BIT BIT(23)
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#define DDR2_MCLKSTOPEN_BIT BIT(30)
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#define DDR2_LPMODEN_BIT BIT(31)
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/*
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* Increase size of DMA-consistent memory region
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*/
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#define CONSISTENT_DMA_SIZE (14<<20)
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#ifndef __ASSEMBLY__
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/*
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* Restrict DMA-able region to workaround silicon bug. The bug
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* restricts buffers available for DMA to video hardware to be
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* below 128M
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*/
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static inline void
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__arch_adjust_zones(int node, unsigned long *size, unsigned long *holes)
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{
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unsigned int sz = (128<<20) >> PAGE_SHIFT;
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if (node != 0)
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sz = 0;
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size[1] = size[0] - sz;
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size[0] = sz;
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}
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#define arch_adjust_zones(node, zone_size, holes) \
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if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(node, zone_size, holes)
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#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1)
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#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20))
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#endif
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#endif /* __ASM_ARCH_MEMORY_H */
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