Russell King 0ca33b4ad9 mmc: sdhci-pxav3: fix higher speed mode capabilities ... Commit 1140011ee9 ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") broke any chance of the SDR50 or DDR50 modes being used. The commit claims that SDR50 and DDR50 require clock adjustments in the SDIO3 Configuration register, which is located via the "conf-sdio3" resource. However, when this resource is given, we fail to read the host capabilities 1 register, resulting in host->caps1 being zero. Hence, both SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50 bits remain zero, disabling the SDR50 and DDR50 modes. The underlying idea in this function appears to be to read the device capabilities, modify them, and set SDHCI_QUIRK_MISSING_CAPS to cause our modified capabilities to be used. Implement exactly that. Fixes: 1140011ee9 ("mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modes") Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Cc: stable@vger.kernel.org # v4.5+ Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>		2016-02-29 11:03:16 +01:00
..
card	mmc: block: shut up "retrying because a re-tune was needed" message	2016-02-29 11:03:08 +01:00
core	mmc: core: report tuning command execution failure reason	2016-02-29 11:03:08 +01:00
host	mmc: sdhci-pxav3: fix higher speed mode capabilities	2016-02-29 11:03:16 +01:00
Kconfig
Makefile	mmc: sdhci-pci: add platform data	2012-01-11 23:58:47 -05:00