Guo Ren 0c8a32eed1 csky: Add memory layout 2.5G(user):1.5G(kernel) ... There are two ways for translating va to pa for csky: - Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk) - Use SSEG0/1 (Simple Segment Mapping) We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1 are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0 to use 2G-2.5G as TLB user mapping. Signed-off-by: Guo Ren <guoren@linux.alibaba.com>		2021-01-12 09:52:40 +08:00
..
asid.c	csky: Add new asid lib code from arm	2019-07-19 14:21:36 +08:00
cachev1.c	csky: Support icache flush without specific instructions	2020-02-21 15:43:24 +08:00
cachev2.c	csky/ftrace: Fixup ftrace_modify_code deadlock without CPU_HAS_ICACHE_INS	2020-03-31 22:15:42 +08:00
context.c	csky: Use generic asid algorithm to implement switch_mm	2019-07-19 14:21:36 +08:00
dma-mapping.c	dma-mapping: merge <linux/dma-noncoherent.h> into <linux/dma-map-ops.h>	2020-10-06 07:07:06 +02:00
fault.c	csky: Add memory layout 2.5G(user):1.5G(kernel)	2021-01-12 09:52:40 +08:00
highmem.c	csky/mm/highmem: Switch to generic kmap atomic	2020-11-06 23:14:56 +01:00
init.c	csky: Add memory layout 2.5G(user):1.5G(kernel)	2021-01-12 09:52:40 +08:00
ioremap.c	csky: use generic ioremap	2019-11-12 11:37:52 +01:00
Makefile	csky: Fixup ftrace modify panic	2020-02-21 15:43:24 +08:00
syscache.c	csky: Add flush_icache_mm to defer flush icache all	2020-02-21 15:43:24 +08:00
tcm.c	csky: Tightly-Coupled Memory or Sram support	2020-02-21 15:43:24 +08:00
tlb.c	mm: don't include asm/pgtable.h if linux/mm.h is already included	2020-06-09 09:39:13 -07:00