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0c551abfa0
By default old pre-3.0 Freescale PCIe controllers reports invalid PCI Class
Code 0x0b20 for PCIe Root Port. It can be seen by lspci -b output on P2020
board which has this pre-3.0 controller:
$ lspci -bvnn
00:00.0 Power PC [0b20]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21)
!!! Invalid class 0b20 for header type 01
Capabilities: [4c] Express Root Port (Slot-), MSI 00
Fix this issue by programming correct PCI Class Code 0x0604 for PCIe Root
Port to the Freescale specific PCIe register 0x474.
With this change lspci -b output is:
$ lspci -bvnn
00:00.0 PCI bridge [0604]: Freescale Semiconductor Inc P2020E [1957:0070] (rev 21) (prog-if 00 [Normal decode])
Capabilities: [4c] Express Root Port (Slot-), MSI 00
Without any "Invalid class" error. So class code was properly reflected
into standard (read-only) PCI register 0x08.
Same fix is already implemented in U-Boot pcie_fsl.c driver in commit:
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.. | ||
ge | ||
xics | ||
xive | ||
6xx-suspend.S | ||
cpm2.c | ||
cpm2_pic.c | ||
cpm2_pic.h | ||
cpm_common.c | ||
cpm_gpio.c | ||
dart.h | ||
dart_iommu.c | ||
dcr-low.S | ||
dcr.c | ||
ehv_pic.c | ||
fsl_gtm.c | ||
fsl_lbc.c | ||
fsl_mpic_err.c | ||
fsl_mpic_timer_wakeup.c | ||
fsl_msi.c | ||
fsl_msi.h | ||
fsl_pci.c | ||
fsl_pci.h | ||
fsl_pmc.c | ||
fsl_rcpm.c | ||
fsl_rio.c | ||
fsl_rio.h | ||
fsl_rmu.c | ||
fsl_soc.c | ||
fsl_soc.h | ||
grackle.c | ||
i8259.c | ||
indirect_pci.c | ||
ipic.c | ||
ipic.h | ||
Kconfig | ||
Makefile | ||
mmio_nvram.c | ||
mpc5xxx_clocks.c | ||
mpic.c | ||
mpic.h | ||
mpic_msgr.c | ||
mpic_msi.c | ||
mpic_timer.c | ||
mpic_u3msi.c | ||
msi_bitmap.c | ||
of_rtc.c | ||
pmi.c | ||
rtc_cmos_setup.c | ||
tsi108_dev.c | ||
tsi108_pci.c | ||
udbg_memcons.c |