mirror of
https://github.com/torvalds/linux
synced 2024-10-26 13:19:27 +00:00
4c13614298
As of this commit, it's guaranteed that if an object is in VRAM that its GPU virtual address will be constant. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
141 lines
3.8 KiB
C
141 lines
3.8 KiB
C
/*
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* Copyright 2010 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "drmP.h"
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#include "nouveau_drv.h"
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#include "nouveau_util.h"
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#include "nouveau_vm.h"
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static void nv84_crypt_isr(struct drm_device *);
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int
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nv84_crypt_create_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *ramin = chan->ramin;
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int ret;
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NV_DEBUG(dev, "ch%d\n", chan->id);
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ret = nouveau_gpuobj_new(dev, chan, 256, 0,
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NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
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&chan->crypt_ctx);
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if (ret)
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return ret;
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nv_wo32(ramin, 0xa0, 0x00190000);
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nv_wo32(ramin, 0xa4, chan->crypt_ctx->vinst + 0xff);
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nv_wo32(ramin, 0xa8, chan->crypt_ctx->vinst);
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nv_wo32(ramin, 0xac, 0);
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nv_wo32(ramin, 0xb0, 0);
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nv_wo32(ramin, 0xb4, 0);
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dev_priv->engine.instmem.flush(dev);
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atomic_inc(&chan->vm->pcrypt_refs);
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return 0;
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}
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void
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nv84_crypt_destroy_context(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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u32 inst;
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if (!chan->crypt_ctx)
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return;
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inst = (chan->ramin->vinst >> 12);
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inst |= 0x80000000;
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/* mark context as invalid if still on the hardware, not
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* doing this causes issues the next time PCRYPT is used,
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* unsurprisingly :)
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*/
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nv_wr32(dev, 0x10200c, 0x00000000);
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if (nv_rd32(dev, 0x102188) == inst)
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nv_mask(dev, 0x102188, 0x80000000, 0x00000000);
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if (nv_rd32(dev, 0x10218c) == inst)
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nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
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nv_wr32(dev, 0x10200c, 0x00000010);
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nouveau_gpuobj_ref(NULL, &chan->crypt_ctx);
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atomic_dec(&chan->vm->pcrypt_refs);
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}
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void
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nv84_crypt_tlb_flush(struct drm_device *dev)
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{
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nv50_vm_flush_engine(dev, 0x0a);
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}
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int
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nv84_crypt_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
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if (!pcrypt->registered) {
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NVOBJ_CLASS(dev, 0x74c1, CRYPT);
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pcrypt->registered = true;
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}
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nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
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nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
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nouveau_irq_register(dev, 14, nv84_crypt_isr);
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nv_wr32(dev, 0x102130, 0xffffffff);
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nv_wr32(dev, 0x102140, 0xffffffbf);
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nv_wr32(dev, 0x10200c, 0x00000010);
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return 0;
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}
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void
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nv84_crypt_fini(struct drm_device *dev)
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{
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nv_wr32(dev, 0x102140, 0x00000000);
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nouveau_irq_unregister(dev, 14);
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}
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static void
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nv84_crypt_isr(struct drm_device *dev)
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{
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u32 stat = nv_rd32(dev, 0x102130);
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u32 mthd = nv_rd32(dev, 0x102190);
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u32 data = nv_rd32(dev, 0x102194);
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u32 inst = nv_rd32(dev, 0x102188) & 0x7fffffff;
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int show = nouveau_ratelimit();
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if (show) {
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NV_INFO(dev, "PCRYPT_INTR: 0x%08x 0x%08x 0x%08x 0x%08x\n",
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stat, mthd, data, inst);
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}
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nv_wr32(dev, 0x102130, stat);
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nv_wr32(dev, 0x10200c, 0x10);
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nv50_fb_vm_trap(dev, show, "PCRYPT");
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}
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