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ae2f5e5ed0
Fix the following build error with binutils 2.25.
CC arch/mips/mm/sc-ip22.o
{standard input}: Assembler messages:
{standard input}:132: Error: number (0x9000000080000000) larger than 32 bits
{standard input}:159: Error: number (0x9000000080000000) larger than 32 bits
{standard input}:200: Error: number (0x9000000080000000) larger than 32 bits
scripts/Makefile.build:293: recipe for target 'arch/mips/mm/sc-ip22.o' failed
make[1]: *** [arch/mips/mm/sc-ip22.o] Error 1
MIPS has used .set mips3 to temporarily switch the assembler to 64 bit
mode in 64 bit kernels virtually forever. Binutils 2.25 broke this
behavious partially by happily accepting 64 bit instructions in .set mips3
mode but puking on 64 bit constants when generating 32 bit ELF. Binutils
2.26 restored the old behaviour again.
Fix build with binutils 2.25 by open coding the offending
dli $1, 0x9000000080000000
as
li $1, 0x9000
dsll $1, $1, 48
which is ugly be the only thing that will build on all binutils vintages.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: stable@vger.kernel.org
191 lines
4.2 KiB
C
191 lines
4.2 KiB
C
/*
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* sc-ip22.c: Indy cache management functions.
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*
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* Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
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* derived from r4xx0.c by David S. Miller (davem@davemloft.net).
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/bcache.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/bootinfo.h>
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#include <asm/sgi/ip22.h>
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#include <asm/sgi/mc.h>
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/* Secondary cache size in bytes, if present. */
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static unsigned long scache_size;
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#undef DEBUG_CACHE
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#define SC_SIZE 0x00080000
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#define SC_LINE 32
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#define CI_MASK (SC_SIZE - SC_LINE)
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#define SC_INDEX(n) ((n) & CI_MASK)
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static inline void indy_sc_wipe(unsigned long first, unsigned long last)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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" .set push # indy_sc_wipe \n"
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" .set noreorder \n"
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" .set mips3 \n"
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" .set noat \n"
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" mfc0 %2, $12 \n"
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" li $1, 0x80 # Go 64 bit \n"
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" mtc0 $1, $12 \n"
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" \n"
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" # \n"
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" # Open code a dli $1, 0x9000000080000000 \n"
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" # \n"
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" # Required because binutils 2.25 will happily accept \n"
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" # 64 bit instructions in .set mips3 mode but puke on \n"
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" # 64 bit constants when generating 32 bit ELF \n"
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" # \n"
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" lui $1,0x9000 \n"
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" dsll $1,$1,0x10 \n"
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" ori $1,$1,0x8000 \n"
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" dsll $1,$1,0x10 \n"
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" \n"
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" or %0, $1 # first line to flush \n"
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" or %1, $1 # last line to flush \n"
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" .set at \n"
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" \n"
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"1: sw $0, 0(%0) \n"
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" bne %0, %1, 1b \n"
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" daddu %0, 32 \n"
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" \n"
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" mtc0 %2, $12 # Back to 32 bit \n"
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" nop # pipeline hazard \n"
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" nop \n"
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" nop \n"
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" nop \n"
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" .set pop \n"
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: "=r" (first), "=r" (last), "=&r" (tmp)
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: "0" (first), "1" (last));
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}
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static void indy_sc_wback_invalidate(unsigned long addr, unsigned long size)
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{
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unsigned long first_line, last_line;
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unsigned long flags;
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#ifdef DEBUG_CACHE
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printk("indy_sc_wback_invalidate[%08lx,%08lx]", addr, size);
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#endif
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/* Catch bad driver code */
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BUG_ON(size == 0);
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/* Which lines to flush? */
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first_line = SC_INDEX(addr);
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last_line = SC_INDEX(addr + size - 1);
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local_irq_save(flags);
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if (first_line <= last_line) {
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indy_sc_wipe(first_line, last_line);
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goto out;
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}
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indy_sc_wipe(first_line, SC_SIZE - SC_LINE);
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indy_sc_wipe(0, last_line);
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out:
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local_irq_restore(flags);
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}
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static void indy_sc_enable(void)
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{
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unsigned long addr, tmp1, tmp2;
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/* This is really cool... */
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#ifdef DEBUG_CACHE
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printk("Enabling R4600 SCACHE\n");
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#endif
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__asm__ __volatile__(
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".set\tpush\n\t"
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".set\tnoreorder\n\t"
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".set\tmips3\n\t"
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"mfc0\t%2, $12\n\t"
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"nop; nop; nop; nop;\n\t"
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"li\t%1, 0x80\n\t"
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"mtc0\t%1, $12\n\t"
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"nop; nop; nop; nop;\n\t"
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"li\t%0, 0x1\n\t"
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"dsll\t%0, 31\n\t"
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"lui\t%1, 0x9000\n\t"
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"dsll32\t%1, 0\n\t"
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"or\t%0, %1, %0\n\t"
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"sb\t$0, 0(%0)\n\t"
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"mtc0\t$0, $12\n\t"
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"nop; nop; nop; nop;\n\t"
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"mtc0\t%2, $12\n\t"
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"nop; nop; nop; nop;\n\t"
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".set\tpop"
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: "=r" (tmp1), "=r" (tmp2), "=r" (addr));
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}
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static void indy_sc_disable(void)
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{
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unsigned long tmp1, tmp2, tmp3;
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#ifdef DEBUG_CACHE
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printk("Disabling R4600 SCACHE\n");
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#endif
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__asm__ __volatile__(
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".set\tpush\n\t"
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".set\tnoreorder\n\t"
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".set\tmips3\n\t"
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"li\t%0, 0x1\n\t"
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"dsll\t%0, 31\n\t"
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"lui\t%1, 0x9000\n\t"
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"dsll32\t%1, 0\n\t"
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"or\t%0, %1, %0\n\t"
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"mfc0\t%2, $12\n\t"
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"nop; nop; nop; nop\n\t"
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"li\t%1, 0x80\n\t"
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"mtc0\t%1, $12\n\t"
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"nop; nop; nop; nop\n\t"
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"sh\t$0, 0(%0)\n\t"
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"mtc0\t$0, $12\n\t"
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"nop; nop; nop; nop\n\t"
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"mtc0\t%2, $12\n\t"
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"nop; nop; nop; nop\n\t"
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".set\tpop"
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: "=r" (tmp1), "=r" (tmp2), "=r" (tmp3));
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}
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static inline int __init indy_sc_probe(void)
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{
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unsigned int size = ip22_eeprom_read(&sgimc->eeprom, 17);
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if (size == 0)
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return 0;
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size <<= PAGE_SHIFT;
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printk(KERN_INFO "R4600/R5000 SCACHE size %dK, linesize 32 bytes.\n",
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size >> 10);
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scache_size = size;
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return 1;
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}
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/* XXX Check with wje if the Indy caches can differentiate between
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writeback + invalidate and just invalidate. */
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static struct bcache_ops indy_sc_ops = {
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.bc_enable = indy_sc_enable,
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.bc_disable = indy_sc_disable,
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.bc_wback_inv = indy_sc_wback_invalidate,
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.bc_inv = indy_sc_wback_invalidate
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};
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void indy_sc_init(void)
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{
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if (indy_sc_probe()) {
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indy_sc_enable();
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bcops = &indy_sc_ops;
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}
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}
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