Mikko Perttunen 0e548d50b9 clk: tegra: Use XUSB-compatible SATA PLL sequence ... Use a sequence for enabling hardware control of the SATA PLL that works both when using the SATA lane with SATA and when using it with XUSB. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>		2014-07-08 11:29:55 +03:00
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clk-audio-sync.c
clk-divider.c	clk: tegra: use max divider if divider overflows	2014-02-17 16:18:34 +02:00
clk-id.h	clk: tegra: Fix xusb_hs_src clock hierarchy	2014-05-22 22:14:52 -07:00
clk-periph-gate.c
clk-periph.c	clk: tegra: Staticize tegra_clk_periph_no_gate_ops	2014-02-23 14:46:05 -08:00
clk-pll-out.c
clk-pll.c	clk: tegra: Use XUSB-compatible SATA PLL sequence	2014-07-08 11:29:55 +03:00
clk-super.c
clk-tegra-audio.c
clk-tegra-fixed.c
clk-tegra-periph.c	clk: tegra: fix vi_sensor clocks on Tegra124	2014-06-25 18:40:07 +03:00
clk-tegra-pmc.c
clk-tegra-super-gen4.c	clk: tegra: cclk_lp has a pllx/2 divider	2014-02-17 16:18:28 +02:00
clk-tegra20.c
clk-tegra30.c
clk-tegra114.c	clk: tegra: fix vi_sensor clocks on Tegra124	2014-06-25 18:40:07 +03:00
clk-tegra124.c	clk: tegra124: init table updates	2014-06-27 16:21:44 +03:00
clk.c	clk: tegra: export clock names for debugging	2014-06-30 16:51:45 +03:00
clk.h
Makefile