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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
169 lines
4.5 KiB
C
169 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2012 Texas Instruments
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* Author: Rob Clark <robdclark@gmail.com>
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*/
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#ifndef __TILCDC_DRV_H__
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#define __TILCDC_DRV_H__
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#include <linux/clk.h>
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#include <linux/cpufreq.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/pm_runtime.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/list.h>
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#include <drm/drmP.h>
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#include <drm/drm_bridge.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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/* Defaulting to pixel clock defined on AM335x */
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#define TILCDC_DEFAULT_MAX_PIXELCLOCK 126000
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/* Defaulting to max width as defined on AM335x */
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#define TILCDC_DEFAULT_MAX_WIDTH 2048
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/*
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* This may need some tweaking, but want to allow at least 1280x1024@60
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* with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
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* be supportable
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*/
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#define TILCDC_DEFAULT_MAX_BANDWIDTH (1280*1024*60)
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struct tilcdc_drm_private {
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void __iomem *mmio;
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struct clk *clk; /* functional clock */
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int rev; /* IP revision */
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/* don't attempt resolutions w/ higher W * H * Hz: */
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uint32_t max_bandwidth;
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/*
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* Pixel Clock will be restricted to some value as
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* defined in the device datasheet measured in KHz
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*/
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uint32_t max_pixelclock;
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/*
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* Max allowable width is limited on a per device basis
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* measured in pixels
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*/
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uint32_t max_width;
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/* Supported pixel formats */
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const uint32_t *pixelformats;
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uint32_t num_pixelformats;
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#ifdef CONFIG_CPU_FREQ
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struct notifier_block freq_transition;
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#endif
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struct workqueue_struct *wq;
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struct drm_crtc *crtc;
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unsigned int num_encoders;
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struct drm_encoder *encoders[8];
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unsigned int num_connectors;
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struct drm_connector *connectors[8];
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struct drm_encoder *external_encoder;
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struct drm_connector *external_connector;
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const struct drm_connector_helper_funcs *connector_funcs;
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bool is_registered;
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bool is_componentized;
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};
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/* Sub-module for display. Since we don't know at compile time what panels
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* or display adapter(s) might be present (for ex, off chip dvi/tfp410,
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* hdmi encoder, various lcd panels), the connector/encoder(s) are split into
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* separate drivers. If they are probed and found to be present, they
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* register themselves with tilcdc_register_module().
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*/
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struct tilcdc_module;
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struct tilcdc_module_ops {
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/* create appropriate encoders/connectors: */
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int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
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#ifdef CONFIG_DEBUG_FS
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/* create debugfs nodes (can be NULL): */
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int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
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#endif
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};
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struct tilcdc_module {
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const char *name;
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struct list_head list;
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const struct tilcdc_module_ops *funcs;
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};
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void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
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const struct tilcdc_module_ops *funcs);
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void tilcdc_module_cleanup(struct tilcdc_module *mod);
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/* Panel config that needs to be set in the crtc, but is not coming from
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* the mode timings. The display module is expected to call
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* tilcdc_crtc_set_panel_info() to set this during modeset.
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*/
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struct tilcdc_panel_info {
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/* AC Bias Pin Frequency */
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uint32_t ac_bias;
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/* AC Bias Pin Transitions per Interrupt */
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uint32_t ac_bias_intrpt;
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/* DMA burst size */
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uint32_t dma_burst_sz;
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/* Bits per pixel */
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uint32_t bpp;
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/* FIFO DMA Request Delay */
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uint32_t fdd;
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/* TFT Alternative Signal Mapping (Only for active) */
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bool tft_alt_mode;
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/* Invert pixel clock */
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bool invert_pxl_clk;
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/* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
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uint32_t sync_edge;
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/* Horizontal and Vertical Sync: Control: 0=ignore */
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uint32_t sync_ctrl;
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/* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
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uint32_t raster_order;
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/* DMA FIFO threshold */
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uint32_t fifo_th;
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};
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#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
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int tilcdc_crtc_create(struct drm_device *dev);
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irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
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void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
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void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
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const struct tilcdc_panel_info *info);
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void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
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bool simulate_vesa_sync);
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int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode);
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int tilcdc_crtc_max_width(struct drm_crtc *crtc);
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void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
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int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
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struct drm_framebuffer *fb,
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struct drm_pending_vblank_event *event);
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int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
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#endif /* __TILCDC_DRV_H__ */
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