linux/drivers/pwm/pwm-tegra.c
Uwe Kleine-König f9a8ee8c8b pwm: Always allocate PWM chip base ID dynamically
Since commit 5e5da1e9fb ("pwm: ab8500: Explicitly allocate pwm chip
base dynamically") all drivers use dynamic ID allocation explicitly. New
drivers are supposed to do the same, so remove support for driver
specified base IDs and drop all assignments in the low-level drivers.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
2021-03-22 11:53:00 +01:00

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// SPDX-License-Identifier: GPL-2.0-or-later
/*
* drivers/pwm/pwm-tegra.c
*
* Tegra pulse-width-modulation controller driver
*
* Copyright (c) 2010-2020, NVIDIA Corporation.
* Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de>
*
* Overview of Tegra Pulse Width Modulator Register:
* 1. 13-bit: Frequency division (SCALE)
* 2. 8-bit : Pulse division (DUTY)
* 3. 1-bit : Enable bit
*
* The PWM clock frequency is divided by 256 before subdividing it based
* on the programmable frequency division value to generate the required
* frequency for PWM output. The maximum output frequency that can be
* achieved is (max rate of source clock) / 256.
* e.g. if source clock rate is 408 MHz, maximum output frequency can be:
* 408 MHz/256 = 1.6 MHz.
* This 1.6 MHz frequency can further be divided using SCALE value in PWM.
*
* PWM pulse width: 8 bits are usable [23:16] for varying pulse width.
* To achieve 100% duty cycle, program Bit [24] of this register to
* 1b1. In which case the other bits [23:16] are set to don't care.
*
* Limitations:
* - When PWM is disabled, the output is driven to inactive.
* - It does not allow the current PWM period to complete and
* stops abruptly.
*
* - If the register is reconfigured while PWM is running,
* it does not complete the currently running period.
*
* - If the user input duty is beyond acceptible limits,
* -EINVAL is returned.
*/
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
#include <linux/pwm.h>
#include <linux/platform_device.h>
#include <linux/pinctrl/consumer.h>
#include <linux/slab.h>
#include <linux/reset.h>
#define PWM_ENABLE (1 << 31)
#define PWM_DUTY_WIDTH 8
#define PWM_DUTY_SHIFT 16
#define PWM_SCALE_WIDTH 13
#define PWM_SCALE_SHIFT 0
struct tegra_pwm_soc {
unsigned int num_channels;
/* Maximum IP frequency for given SoCs */
unsigned long max_frequency;
};
struct tegra_pwm_chip {
struct pwm_chip chip;
struct device *dev;
struct clk *clk;
struct reset_control*rst;
unsigned long clk_rate;
unsigned long min_period_ns;
void __iomem *regs;
const struct tegra_pwm_soc *soc;
};
static inline struct tegra_pwm_chip *to_tegra_pwm_chip(struct pwm_chip *chip)
{
return container_of(chip, struct tegra_pwm_chip, chip);
}
static inline u32 pwm_readl(struct tegra_pwm_chip *chip, unsigned int num)
{
return readl(chip->regs + (num << 4));
}
static inline void pwm_writel(struct tegra_pwm_chip *chip, unsigned int num,
unsigned long val)
{
writel(val, chip->regs + (num << 4));
}
static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
int duty_ns, int period_ns)
{
struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
unsigned long long c = duty_ns, hz;
unsigned long rate, required_clk_rate;
u32 val = 0;
int err;
/*
* Convert from duty_ns / period_ns to a fixed number of duty ticks
* per (1 << PWM_DUTY_WIDTH) cycles and make sure to round to the
* nearest integer during division.
*/
c *= (1 << PWM_DUTY_WIDTH);
c = DIV_ROUND_CLOSEST_ULL(c, period_ns);
val = (u32)c << PWM_DUTY_SHIFT;
/*
* min period = max clock limit >> PWM_DUTY_WIDTH
*/
if (period_ns < pc->min_period_ns)
return -EINVAL;
/*
* Compute the prescaler value for which (1 << PWM_DUTY_WIDTH)
* cycles at the PWM clock rate will take period_ns nanoseconds.
*
* num_channels: If single instance of PWM controller has multiple
* channels (e.g. Tegra210 or older) then it is not possible to
* configure separate clock rates to each of the channels, in such
* case the value stored during probe will be referred.
*
* If every PWM controller instance has one channel respectively, i.e.
* nums_channels == 1 then only the clock rate can be modified
* dynamically (e.g. Tegra186 or Tegra194).
*/
if (pc->soc->num_channels == 1) {
/*
* Rate is multiplied with 2^PWM_DUTY_WIDTH so that it matches
* with the maximum possible rate that the controller can
* provide. Any further lower value can be derived by setting
* PFM bits[0:12].
*
* required_clk_rate is a reference rate for source clock and
* it is derived based on user requested period. By setting the
* source clock rate as required_clk_rate, PWM controller will
* be able to configure the requested period.
*/
required_clk_rate =
(NSEC_PER_SEC / period_ns) << PWM_DUTY_WIDTH;
err = clk_set_rate(pc->clk, required_clk_rate);
if (err < 0)
return -EINVAL;
/* Store the new rate for further references */
pc->clk_rate = clk_get_rate(pc->clk);
}
rate = pc->clk_rate >> PWM_DUTY_WIDTH;
/* Consider precision in PWM_SCALE_WIDTH rate calculation */
hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns);
rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz);
/*
* Since the actual PWM divider is the register's frequency divider
* field plus 1, we need to decrement to get the correct value to
* write to the register.
*/
if (rate > 0)
rate--;
/*
* Make sure that the rate will fit in the register's frequency
* divider field.
*/
if (rate >> PWM_SCALE_WIDTH)
return -EINVAL;
val |= rate << PWM_SCALE_SHIFT;
/*
* If the PWM channel is disabled, make sure to turn on the clock
* before writing the register. Otherwise, keep it enabled.
*/
if (!pwm_is_enabled(pwm)) {
err = clk_prepare_enable(pc->clk);
if (err < 0)
return err;
} else
val |= PWM_ENABLE;
pwm_writel(pc, pwm->hwpwm, val);
/*
* If the PWM is not enabled, turn the clock off again to save power.
*/
if (!pwm_is_enabled(pwm))
clk_disable_unprepare(pc->clk);
return 0;
}
static int tegra_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
int rc = 0;
u32 val;
rc = clk_prepare_enable(pc->clk);
if (rc < 0)
return rc;
val = pwm_readl(pc, pwm->hwpwm);
val |= PWM_ENABLE;
pwm_writel(pc, pwm->hwpwm, val);
return 0;
}
static void tegra_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
{
struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip);
u32 val;
val = pwm_readl(pc, pwm->hwpwm);
val &= ~PWM_ENABLE;
pwm_writel(pc, pwm->hwpwm, val);
clk_disable_unprepare(pc->clk);
}
static const struct pwm_ops tegra_pwm_ops = {
.config = tegra_pwm_config,
.enable = tegra_pwm_enable,
.disable = tegra_pwm_disable,
.owner = THIS_MODULE,
};
static int tegra_pwm_probe(struct platform_device *pdev)
{
struct tegra_pwm_chip *pwm;
int ret;
pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
if (!pwm)
return -ENOMEM;
pwm->soc = of_device_get_match_data(&pdev->dev);
pwm->dev = &pdev->dev;
pwm->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(pwm->regs))
return PTR_ERR(pwm->regs);
platform_set_drvdata(pdev, pwm);
pwm->clk = devm_clk_get(&pdev->dev, NULL);
if (IS_ERR(pwm->clk))
return PTR_ERR(pwm->clk);
/* Set maximum frequency of the IP */
ret = clk_set_rate(pwm->clk, pwm->soc->max_frequency);
if (ret < 0) {
dev_err(&pdev->dev, "Failed to set max frequency: %d\n", ret);
return ret;
}
/*
* The requested and configured frequency may differ due to
* clock register resolutions. Get the configured frequency
* so that PWM period can be calculated more accurately.
*/
pwm->clk_rate = clk_get_rate(pwm->clk);
/* Set minimum limit of PWM period for the IP */
pwm->min_period_ns =
(NSEC_PER_SEC / (pwm->soc->max_frequency >> PWM_DUTY_WIDTH)) + 1;
pwm->rst = devm_reset_control_get_exclusive(&pdev->dev, "pwm");
if (IS_ERR(pwm->rst)) {
ret = PTR_ERR(pwm->rst);
dev_err(&pdev->dev, "Reset control is not found: %d\n", ret);
return ret;
}
reset_control_deassert(pwm->rst);
pwm->chip.dev = &pdev->dev;
pwm->chip.ops = &tegra_pwm_ops;
pwm->chip.npwm = pwm->soc->num_channels;
ret = pwmchip_add(&pwm->chip);
if (ret < 0) {
dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
reset_control_assert(pwm->rst);
return ret;
}
return 0;
}
static int tegra_pwm_remove(struct platform_device *pdev)
{
struct tegra_pwm_chip *pc = platform_get_drvdata(pdev);
unsigned int i;
int err;
if (WARN_ON(!pc))
return -ENODEV;
err = clk_prepare_enable(pc->clk);
if (err < 0)
return err;
for (i = 0; i < pc->chip.npwm; i++) {
struct pwm_device *pwm = &pc->chip.pwms[i];
if (!pwm_is_enabled(pwm))
if (clk_prepare_enable(pc->clk) < 0)
continue;
pwm_writel(pc, i, 0);
clk_disable_unprepare(pc->clk);
}
reset_control_assert(pc->rst);
clk_disable_unprepare(pc->clk);
return pwmchip_remove(&pc->chip);
}
#ifdef CONFIG_PM_SLEEP
static int tegra_pwm_suspend(struct device *dev)
{
return pinctrl_pm_select_sleep_state(dev);
}
static int tegra_pwm_resume(struct device *dev)
{
return pinctrl_pm_select_default_state(dev);
}
#endif
static const struct tegra_pwm_soc tegra20_pwm_soc = {
.num_channels = 4,
.max_frequency = 48000000UL,
};
static const struct tegra_pwm_soc tegra186_pwm_soc = {
.num_channels = 1,
.max_frequency = 102000000UL,
};
static const struct tegra_pwm_soc tegra194_pwm_soc = {
.num_channels = 1,
.max_frequency = 408000000UL,
};
static const struct of_device_id tegra_pwm_of_match[] = {
{ .compatible = "nvidia,tegra20-pwm", .data = &tegra20_pwm_soc },
{ .compatible = "nvidia,tegra186-pwm", .data = &tegra186_pwm_soc },
{ .compatible = "nvidia,tegra194-pwm", .data = &tegra194_pwm_soc },
{ }
};
MODULE_DEVICE_TABLE(of, tegra_pwm_of_match);
static const struct dev_pm_ops tegra_pwm_pm_ops = {
SET_SYSTEM_SLEEP_PM_OPS(tegra_pwm_suspend, tegra_pwm_resume)
};
static struct platform_driver tegra_pwm_driver = {
.driver = {
.name = "tegra-pwm",
.of_match_table = tegra_pwm_of_match,
.pm = &tegra_pwm_pm_ops,
},
.probe = tegra_pwm_probe,
.remove = tegra_pwm_remove,
};
module_platform_driver(tegra_pwm_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Sandipan Patra <spatra@nvidia.com>");
MODULE_DESCRIPTION("Tegra PWM controller driver");
MODULE_ALIAS("platform:tegra-pwm");