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f300ba2d1e
MSS change on active QPs is not supported. Store new MSS value for new QPs only. Remove code to modify MSS on the fly. This also resolves a crash on QP modify to QP 0. BUG: unable to handle kernel NULL pointer dereference at 0000000000000008 IP: i40iw_sc_qp_modify+0x22/0x280 [i40iw] Oops: 0000 [#1] SMP KASAN CPU: 2 PID: 1236 Comm: kworker/u16:4 Not tainted 4.12.0-rc1 #5 Hardware name: Gigabyte Technology Co., Ltd. To be filled by O.E.M./Q87M-D2H, BIOS F7 01/17/2014 Workqueue: l2params i40iw_l2params_worker [i40iw] task: ffff88070f5a9b40 task.stack: ffff88070f5a0000 RIP: 0010:i40iw_sc_qp_modify+0x22/0x280 [i40iw] ... Call Trace: i40iw_exec_cqp_cmd+0x2ce/0x410 [i40iw] ? _raw_spin_lock_irqsave+0x6f/0x80 ? i40iw_process_cqp_cmd+0x1d/0x80 [i40iw] i40iw_process_cqp_cmd+0x7c/0x80 [i40iw] i40iw_handle_cqp_op+0x2f/0x200 [i40iw] ? trace_hardirqs_off+0xd/0x10 ? _raw_spin_unlock_irqrestore+0x46/0x50 i40iw_hw_modify_qp+0x5e/0x90 [i40iw] i40iw_qp_mss_modify+0x52/0x60 [i40iw] i40iw_change_l2params+0x145/0x160 [i40iw] i40iw_l2params_worker+0x1f/0x40 [i40iw] process_one_work+0x1f5/0x650 ? process_one_work+0x161/0x650 worker_thread+0x48/0x3b0 kthread+0x112/0x150 ? process_one_work+0x650/0x650 ? kthread_create_on_node+0x40/0x40 ret_from_fork+0x2e/0x40 Code: 2e 0f 1f 84 00 00 00 00 00 55 48 89 e5 41 56 41 55 41 89 cd 41 54 49 89 fc 53 48 89 f3 48 89 d6 48 83 ec 08 48 8b 87 10 01 00 00 <48> 8b 40 08 4c 8b b0 40 04 00 00 4c 89 f7 e8 1b e5 ff ff 48 85 RIP: i40iw_sc_qp_modify+0x22/0x280 [i40iw] RSP: ffff88070f5a7c28 CR2: 0000000000000008 ---[ end trace 77a405931e296060 ]--- Reported-by: Stefan Assmann <sassmann@redhat.com> Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
218 lines
8.5 KiB
C
218 lines
8.5 KiB
C
/*******************************************************************************
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*
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* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenFabrics.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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*******************************************************************************/
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#ifndef I40IW_OSDEP_H
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#define I40IW_OSDEP_H
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/bitops.h>
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#include <net/tcp.h>
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#include <crypto/hash.h>
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/* get readq/writeq support for 32 bit kernels, use the low-first version */
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#include <linux/io-64-nonatomic-lo-hi.h>
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#define STATS_TIMER_DELAY 1000
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static inline void set_64bit_val(u64 *wqe_words, u32 byte_index, u64 value)
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{
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wqe_words[byte_index >> 3] = value;
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}
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/**
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* set_32bit_val - set 32 value to hw wqe
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* @wqe_words: wqe addr to write
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* @byte_index: index in wqe
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* @value: value to write
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**/
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static inline void set_32bit_val(u32 *wqe_words, u32 byte_index, u32 value)
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{
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wqe_words[byte_index >> 2] = value;
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}
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/**
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* get_64bit_val - read 64 bit value from wqe
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* @wqe_words: wqe addr
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* @byte_index: index to read from
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* @value: read value
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**/
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static inline void get_64bit_val(u64 *wqe_words, u32 byte_index, u64 *value)
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{
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*value = wqe_words[byte_index >> 3];
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}
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/**
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* get_32bit_val - read 32 bit value from wqe
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* @wqe_words: wqe addr
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* @byte_index: index to reaad from
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* @value: return 32 bit value
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**/
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static inline void get_32bit_val(u32 *wqe_words, u32 byte_index, u32 *value)
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{
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*value = wqe_words[byte_index >> 2];
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}
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struct i40iw_dma_mem {
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void *va;
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dma_addr_t pa;
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u32 size;
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} __packed;
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struct i40iw_virt_mem {
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void *va;
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u32 size;
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} __packed;
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#define i40iw_debug(h, m, s, ...) \
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do { \
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if (((m) & (h)->debug_mask)) \
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pr_info("i40iw " s, ##__VA_ARGS__); \
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} while (0)
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#define i40iw_flush(a) readl((a)->hw_addr + I40E_GLGEN_STAT)
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#define I40E_GLHMC_VFSDCMD(_i) (0x000C8000 + ((_i) * 4)) \
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/* _i=0...31 */
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#define I40E_GLHMC_VFSDCMD_MAX_INDEX 31
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#define I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT 0
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#define I40E_GLHMC_VFSDCMD_PMSDIDX_MASK (0xFFF \
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<< I40E_GLHMC_VFSDCMD_PMSDIDX_SHIFT)
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#define I40E_GLHMC_VFSDCMD_PF_SHIFT 16
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#define I40E_GLHMC_VFSDCMD_PF_MASK (0xF << I40E_GLHMC_VFSDCMD_PF_SHIFT)
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#define I40E_GLHMC_VFSDCMD_VF_SHIFT 20
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#define I40E_GLHMC_VFSDCMD_VF_MASK (0x1FF << I40E_GLHMC_VFSDCMD_VF_SHIFT)
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#define I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT 29
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#define I40E_GLHMC_VFSDCMD_PMF_TYPE_MASK (0x3 \
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<< I40E_GLHMC_VFSDCMD_PMF_TYPE_SHIFT)
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#define I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT 31
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#define I40E_GLHMC_VFSDCMD_PMSDWR_MASK (0x1 << I40E_GLHMC_VFSDCMD_PMSDWR_SHIFT)
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#define I40E_GLHMC_VFSDDATAHIGH(_i) (0x000C8200 + ((_i) * 4)) \
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/* _i=0...31 */
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#define I40E_GLHMC_VFSDDATAHIGH_MAX_INDEX 31
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#define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT 0
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#define I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_MASK (0xFFFFFFFF \
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<< I40E_GLHMC_VFSDDATAHIGH_PMSDDATAHIGH_SHIFT)
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#define I40E_GLHMC_VFSDDATALOW(_i) (0x000C8100 + ((_i) * 4)) \
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/* _i=0...31 */
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#define I40E_GLHMC_VFSDDATALOW_MAX_INDEX 31
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#define I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT 0
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#define I40E_GLHMC_VFSDDATALOW_PMSDVALID_MASK (0x1 \
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<< I40E_GLHMC_VFSDDATALOW_PMSDVALID_SHIFT)
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#define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT 1
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#define I40E_GLHMC_VFSDDATALOW_PMSDTYPE_MASK (0x1 \
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<< I40E_GLHMC_VFSDDATALOW_PMSDTYPE_SHIFT)
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#define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT 2
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#define I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_MASK (0x3FF \
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<< I40E_GLHMC_VFSDDATALOW_PMSDBPCOUNT_SHIFT)
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#define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT 12
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#define I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_MASK (0xFFFFF \
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<< I40E_GLHMC_VFSDDATALOW_PMSDDATALOW_SHIFT)
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#define I40E_GLPE_FWLDSTATUS 0x0000D200
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#define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT 0
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#define I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_MASK (0x1 \
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<< I40E_GLPE_FWLDSTATUS_LOAD_REQUESTED_SHIFT)
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#define I40E_GLPE_FWLDSTATUS_DONE_SHIFT 1
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#define I40E_GLPE_FWLDSTATUS_DONE_MASK (0x1 << I40E_GLPE_FWLDSTATUS_DONE_SHIFT)
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#define I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT 2
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#define I40E_GLPE_FWLDSTATUS_CQP_FAIL_MASK (0x1 \
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<< I40E_GLPE_FWLDSTATUS_CQP_FAIL_SHIFT)
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#define I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT 3
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#define I40E_GLPE_FWLDSTATUS_TEP_FAIL_MASK (0x1 \
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<< I40E_GLPE_FWLDSTATUS_TEP_FAIL_SHIFT)
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#define I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT 4
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#define I40E_GLPE_FWLDSTATUS_OOP_FAIL_MASK (0x1 \
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<< I40E_GLPE_FWLDSTATUS_OOP_FAIL_SHIFT)
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struct i40iw_sc_dev;
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struct i40iw_sc_qp;
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struct i40iw_puda_buf;
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struct i40iw_puda_completion_info;
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struct i40iw_update_sds_info;
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struct i40iw_hmc_fcn_info;
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struct i40iw_virtchnl_work_info;
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struct i40iw_manage_vf_pble_info;
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struct i40iw_device;
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struct i40iw_hmc_info;
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struct i40iw_hw;
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u8 __iomem *i40iw_get_hw_addr(void *dev);
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void i40iw_ieq_mpa_crc_ae(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp);
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enum i40iw_status_code i40iw_vf_wait_vchnl_resp(struct i40iw_sc_dev *dev);
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bool i40iw_vf_clear_to_send(struct i40iw_sc_dev *dev);
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enum i40iw_status_code i40iw_ieq_check_mpacrc(struct shash_desc *desc, void *addr,
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u32 length, u32 value);
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struct i40iw_sc_qp *i40iw_ieq_get_qp(struct i40iw_sc_dev *dev, struct i40iw_puda_buf *buf);
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void i40iw_ieq_update_tcpip_info(struct i40iw_puda_buf *buf, u16 length, u32 seqnum);
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void i40iw_free_hash_desc(struct shash_desc *);
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enum i40iw_status_code i40iw_init_hash_desc(struct shash_desc **);
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enum i40iw_status_code i40iw_puda_get_tcpip_info(struct i40iw_puda_completion_info *info,
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struct i40iw_puda_buf *buf);
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enum i40iw_status_code i40iw_cqp_sds_cmd(struct i40iw_sc_dev *dev,
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struct i40iw_update_sds_info *info);
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enum i40iw_status_code i40iw_cqp_manage_hmc_fcn_cmd(struct i40iw_sc_dev *dev,
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struct i40iw_hmc_fcn_info *hmcfcninfo);
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enum i40iw_status_code i40iw_cqp_query_fpm_values_cmd(struct i40iw_sc_dev *dev,
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struct i40iw_dma_mem *values_mem,
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u8 hmc_fn_id);
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enum i40iw_status_code i40iw_cqp_commit_fpm_values_cmd(struct i40iw_sc_dev *dev,
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struct i40iw_dma_mem *values_mem,
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u8 hmc_fn_id);
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enum i40iw_status_code i40iw_alloc_query_fpm_buf(struct i40iw_sc_dev *dev,
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struct i40iw_dma_mem *mem);
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enum i40iw_status_code i40iw_cqp_manage_vf_pble_bp(struct i40iw_sc_dev *dev,
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struct i40iw_manage_vf_pble_info *info);
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void i40iw_cqp_spawn_worker(struct i40iw_sc_dev *dev,
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struct i40iw_virtchnl_work_info *work_info, u32 iw_vf_idx);
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void *i40iw_remove_head(struct list_head *list);
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void i40iw_qp_suspend_resume(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp, bool suspend);
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void i40iw_term_modify_qp(struct i40iw_sc_qp *qp, u8 next_state, u8 term, u8 term_len);
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void i40iw_terminate_done(struct i40iw_sc_qp *qp, int timeout_occurred);
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void i40iw_terminate_start_timer(struct i40iw_sc_qp *qp);
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void i40iw_terminate_del_timer(struct i40iw_sc_qp *qp);
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enum i40iw_status_code i40iw_hw_manage_vf_pble_bp(struct i40iw_device *iwdev,
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struct i40iw_manage_vf_pble_info *info,
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bool wait);
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struct i40iw_sc_vsi;
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void i40iw_hw_stats_start_timer(struct i40iw_sc_vsi *vsi);
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void i40iw_hw_stats_stop_timer(struct i40iw_sc_vsi *vsi);
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#define i40iw_mmiowb() mmiowb()
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void i40iw_wr32(struct i40iw_hw *hw, u32 reg, u32 value);
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u32 i40iw_rd32(struct i40iw_hw *hw, u32 reg);
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#endif /* _I40IW_OSDEP_H_ */
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