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With the recent feature added to enable perf events to use pseudo NMIs as interrupts on platforms which support GICv3 or later, its now been possible to enable hard lockup detector (or NMI watchdog) on arm64 platforms. So enable corresponding support. One thing to note here is that normally lockup detector is initialized just after the early initcalls but PMU on arm64 comes up much later as device_initcall(). To cope with that, override arch_perf_nmi_is_available() to let the watchdog framework know PMU not ready, and inform the framework to re-initialize lockup detection once PMU has been initialized. [dianders@chromium.org: only HAVE_HARDLOCKUP_DETECTOR_PERF if the PMU config is enabled] Link: https://lkml.kernel.org/r/20230523073952.1.I60217a63acc35621e13f10be16c0cd7c363caf8c@changeid Link: https://lkml.kernel.org/r/20230519101840.v5.18.Ia44852044cdcb074f387e80df6b45e892965d4a1@changeid Co-developed-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Co-developed-by: Pingfan Liu <kernelfans@gmail.com> Signed-off-by: Pingfan Liu <kernelfans@gmail.com> Signed-off-by: Lecopzer Chen <lecopzer.chen@mediatek.com> Signed-off-by: Douglas Anderson <dianders@chromium.org> Cc: Andi Kleen <ak@linux.intel.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Colin Cross <ccross@android.com> Cc: Daniel Thompson <daniel.thompson@linaro.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Guenter Roeck <groeck@chromium.org> Cc: Ian Rogers <irogers@google.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Masayoshi Mizuma <msys.mizuma@gmail.com> Cc: Matthias Kaehlcke <mka@chromium.org> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Petr Mladek <pmladek@suse.com> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com> Cc: Ricardo Neri <ricardo.neri@intel.com> Cc: Stephane Eranian <eranian@google.com> Cc: Stephen Boyd <swboyd@chromium.org> Cc: Tzung-Bi Shih <tzungbi@chromium.org> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
37 lines
1.2 KiB
C
37 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0
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#include <linux/nmi.h>
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#include <linux/cpufreq.h>
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#include <linux/perf/arm_pmu.h>
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/*
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* Safe maximum CPU frequency in case a particular platform doesn't implement
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* cpufreq driver. Although, architecture doesn't put any restrictions on
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* maximum frequency but 5 GHz seems to be safe maximum given the available
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* Arm CPUs in the market which are clocked much less than 5 GHz. On the other
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* hand, we can't make it much higher as it would lead to a large hard-lockup
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* detection timeout on parts which are running slower (eg. 1GHz on
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* Developerbox) and doesn't possess a cpufreq driver.
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*/
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#define SAFE_MAX_CPU_FREQ 5000000000UL // 5 GHz
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u64 hw_nmi_get_sample_period(int watchdog_thresh)
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{
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unsigned int cpu = smp_processor_id();
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unsigned long max_cpu_freq;
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max_cpu_freq = cpufreq_get_hw_max_freq(cpu) * 1000UL;
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if (!max_cpu_freq)
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max_cpu_freq = SAFE_MAX_CPU_FREQ;
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return (u64)max_cpu_freq * watchdog_thresh;
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}
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bool __init arch_perf_nmi_is_available(void)
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{
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/*
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* hardlockup_detector_perf_init() will success even if Pseudo-NMI turns off,
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* however, the pmu interrupts will act like a normal interrupt instead of
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* NMI and the hardlockup detector would be broken.
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*/
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return arm_pmu_irq_is_nmi();
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}
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