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aafa85e71a
This patch adds three main functions for DAI master mode: set_dai_fmt(), set_dai_sysclk() and set_dai_tdm_slot(), and one essential baud clock accordingly. After appending this patch, the fsl_ssi driver on i.MX series has the ability to derive LRCLK and BCLK from baud clock source so as to support some audio Codecs which can only be used in slave mode. Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>
211 lines
8.3 KiB
C
211 lines
8.3 KiB
C
/*
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* fsl_ssi.h - ALSA SSI interface for the Freescale MPC8610 SoC
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed
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* under the terms of the GNU General Public License version 2. This
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* program is licensed "as is" without any warranty of any kind, whether
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* express or implied.
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*/
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#ifndef _MPC8610_I2S_H
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#define _MPC8610_I2S_H
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/* SSI Register Map */
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struct ccsr_ssi {
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__be32 stx0; /* 0x.0000 - SSI Transmit Data Register 0 */
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__be32 stx1; /* 0x.0004 - SSI Transmit Data Register 1 */
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__be32 srx0; /* 0x.0008 - SSI Receive Data Register 0 */
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__be32 srx1; /* 0x.000C - SSI Receive Data Register 1 */
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__be32 scr; /* 0x.0010 - SSI Control Register */
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__be32 sisr; /* 0x.0014 - SSI Interrupt Status Register Mixed */
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__be32 sier; /* 0x.0018 - SSI Interrupt Enable Register */
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__be32 stcr; /* 0x.001C - SSI Transmit Configuration Register */
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__be32 srcr; /* 0x.0020 - SSI Receive Configuration Register */
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__be32 stccr; /* 0x.0024 - SSI Transmit Clock Control Register */
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__be32 srccr; /* 0x.0028 - SSI Receive Clock Control Register */
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__be32 sfcsr; /* 0x.002C - SSI FIFO Control/Status Register */
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__be32 str; /* 0x.0030 - SSI Test Register */
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__be32 sor; /* 0x.0034 - SSI Option Register */
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__be32 sacnt; /* 0x.0038 - SSI AC97 Control Register */
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__be32 sacadd; /* 0x.003C - SSI AC97 Command Address Register */
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__be32 sacdat; /* 0x.0040 - SSI AC97 Command Data Register */
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__be32 satag; /* 0x.0044 - SSI AC97 Tag Register */
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__be32 stmsk; /* 0x.0048 - SSI Transmit Time Slot Mask Register */
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__be32 srmsk; /* 0x.004C - SSI Receive Time Slot Mask Register */
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__be32 saccst; /* 0x.0050 - SSI AC97 Channel Status Register */
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__be32 saccen; /* 0x.0054 - SSI AC97 Channel Enable Register */
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__be32 saccdis; /* 0x.0058 - SSI AC97 Channel Disable Register */
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};
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#define CCSR_SSI_SCR_RFR_CLK_DIS 0x00000800
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#define CCSR_SSI_SCR_TFR_CLK_DIS 0x00000400
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#define CCSR_SSI_SCR_TCH_EN 0x00000100
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#define CCSR_SSI_SCR_SYS_CLK_EN 0x00000080
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#define CCSR_SSI_SCR_I2S_MODE_MASK 0x00000060
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#define CCSR_SSI_SCR_I2S_MODE_NORMAL 0x00000000
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#define CCSR_SSI_SCR_I2S_MODE_MASTER 0x00000020
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#define CCSR_SSI_SCR_I2S_MODE_SLAVE 0x00000040
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#define CCSR_SSI_SCR_SYN 0x00000010
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#define CCSR_SSI_SCR_NET 0x00000008
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#define CCSR_SSI_SCR_RE 0x00000004
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#define CCSR_SSI_SCR_TE 0x00000002
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#define CCSR_SSI_SCR_SSIEN 0x00000001
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#define CCSR_SSI_SISR_RFRC 0x01000000
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#define CCSR_SSI_SISR_TFRC 0x00800000
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#define CCSR_SSI_SISR_CMDAU 0x00040000
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#define CCSR_SSI_SISR_CMDDU 0x00020000
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#define CCSR_SSI_SISR_RXT 0x00010000
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#define CCSR_SSI_SISR_RDR1 0x00008000
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#define CCSR_SSI_SISR_RDR0 0x00004000
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#define CCSR_SSI_SISR_TDE1 0x00002000
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#define CCSR_SSI_SISR_TDE0 0x00001000
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#define CCSR_SSI_SISR_ROE1 0x00000800
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#define CCSR_SSI_SISR_ROE0 0x00000400
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#define CCSR_SSI_SISR_TUE1 0x00000200
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#define CCSR_SSI_SISR_TUE0 0x00000100
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#define CCSR_SSI_SISR_TFS 0x00000080
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#define CCSR_SSI_SISR_RFS 0x00000040
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#define CCSR_SSI_SISR_TLS 0x00000020
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#define CCSR_SSI_SISR_RLS 0x00000010
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#define CCSR_SSI_SISR_RFF1 0x00000008
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#define CCSR_SSI_SISR_RFF0 0x00000004
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#define CCSR_SSI_SISR_TFE1 0x00000002
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#define CCSR_SSI_SISR_TFE0 0x00000001
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#define CCSR_SSI_SIER_RFRC_EN 0x01000000
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#define CCSR_SSI_SIER_TFRC_EN 0x00800000
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#define CCSR_SSI_SIER_RDMAE 0x00400000
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#define CCSR_SSI_SIER_RIE 0x00200000
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#define CCSR_SSI_SIER_TDMAE 0x00100000
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#define CCSR_SSI_SIER_TIE 0x00080000
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#define CCSR_SSI_SIER_CMDAU_EN 0x00040000
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#define CCSR_SSI_SIER_CMDDU_EN 0x00020000
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#define CCSR_SSI_SIER_RXT_EN 0x00010000
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#define CCSR_SSI_SIER_RDR1_EN 0x00008000
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#define CCSR_SSI_SIER_RDR0_EN 0x00004000
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#define CCSR_SSI_SIER_TDE1_EN 0x00002000
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#define CCSR_SSI_SIER_TDE0_EN 0x00001000
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#define CCSR_SSI_SIER_ROE1_EN 0x00000800
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#define CCSR_SSI_SIER_ROE0_EN 0x00000400
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#define CCSR_SSI_SIER_TUE1_EN 0x00000200
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#define CCSR_SSI_SIER_TUE0_EN 0x00000100
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#define CCSR_SSI_SIER_TFS_EN 0x00000080
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#define CCSR_SSI_SIER_RFS_EN 0x00000040
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#define CCSR_SSI_SIER_TLS_EN 0x00000020
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#define CCSR_SSI_SIER_RLS_EN 0x00000010
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#define CCSR_SSI_SIER_RFF1_EN 0x00000008
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#define CCSR_SSI_SIER_RFF0_EN 0x00000004
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#define CCSR_SSI_SIER_TFE1_EN 0x00000002
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#define CCSR_SSI_SIER_TFE0_EN 0x00000001
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#define CCSR_SSI_STCR_TXBIT0 0x00000200
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#define CCSR_SSI_STCR_TFEN1 0x00000100
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#define CCSR_SSI_STCR_TFEN0 0x00000080
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#define CCSR_SSI_STCR_TFDIR 0x00000040
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#define CCSR_SSI_STCR_TXDIR 0x00000020
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#define CCSR_SSI_STCR_TSHFD 0x00000010
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#define CCSR_SSI_STCR_TSCKP 0x00000008
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#define CCSR_SSI_STCR_TFSI 0x00000004
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#define CCSR_SSI_STCR_TFSL 0x00000002
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#define CCSR_SSI_STCR_TEFS 0x00000001
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#define CCSR_SSI_SRCR_RXEXT 0x00000400
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#define CCSR_SSI_SRCR_RXBIT0 0x00000200
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#define CCSR_SSI_SRCR_RFEN1 0x00000100
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#define CCSR_SSI_SRCR_RFEN0 0x00000080
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#define CCSR_SSI_SRCR_RFDIR 0x00000040
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#define CCSR_SSI_SRCR_RXDIR 0x00000020
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#define CCSR_SSI_SRCR_RSHFD 0x00000010
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#define CCSR_SSI_SRCR_RSCKP 0x00000008
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#define CCSR_SSI_SRCR_RFSI 0x00000004
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#define CCSR_SSI_SRCR_RFSL 0x00000002
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#define CCSR_SSI_SRCR_REFS 0x00000001
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/* STCCR and SRCCR */
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#define CCSR_SSI_SxCCR_DIV2_SHIFT 18
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#define CCSR_SSI_SxCCR_DIV2 0x00040000
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#define CCSR_SSI_SxCCR_PSR_SHIFT 17
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#define CCSR_SSI_SxCCR_PSR 0x00020000
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#define CCSR_SSI_SxCCR_WL_SHIFT 13
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#define CCSR_SSI_SxCCR_WL_MASK 0x0001E000
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#define CCSR_SSI_SxCCR_WL(x) \
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(((((x) / 2) - 1) << CCSR_SSI_SxCCR_WL_SHIFT) & CCSR_SSI_SxCCR_WL_MASK)
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#define CCSR_SSI_SxCCR_DC_SHIFT 8
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#define CCSR_SSI_SxCCR_DC_MASK 0x00001F00
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#define CCSR_SSI_SxCCR_DC(x) \
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((((x) - 1) << CCSR_SSI_SxCCR_DC_SHIFT) & CCSR_SSI_SxCCR_DC_MASK)
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#define CCSR_SSI_SxCCR_PM_SHIFT 0
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#define CCSR_SSI_SxCCR_PM_MASK 0x000000FF
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#define CCSR_SSI_SxCCR_PM(x) \
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((((x) - 1) << CCSR_SSI_SxCCR_PM_SHIFT) & CCSR_SSI_SxCCR_PM_MASK)
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/*
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* The xFCNT bits are read-only, and the xFWM bits are read/write. Use the
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* CCSR_SSI_SFCSR_xFCNTy() macros to read the FIFO counters, and use the
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* CCSR_SSI_SFCSR_xFWMy() macros to set the watermarks.
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*/
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#define CCSR_SSI_SFCSR_RFCNT1_SHIFT 28
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#define CCSR_SSI_SFCSR_RFCNT1_MASK 0xF0000000
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#define CCSR_SSI_SFCSR_RFCNT1(x) \
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(((x) & CCSR_SSI_SFCSR_RFCNT1_MASK) >> CCSR_SSI_SFCSR_RFCNT1_SHIFT)
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#define CCSR_SSI_SFCSR_TFCNT1_SHIFT 24
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#define CCSR_SSI_SFCSR_TFCNT1_MASK 0x0F000000
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#define CCSR_SSI_SFCSR_TFCNT1(x) \
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(((x) & CCSR_SSI_SFCSR_TFCNT1_MASK) >> CCSR_SSI_SFCSR_TFCNT1_SHIFT)
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#define CCSR_SSI_SFCSR_RFWM1_SHIFT 20
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#define CCSR_SSI_SFCSR_RFWM1_MASK 0x00F00000
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#define CCSR_SSI_SFCSR_RFWM1(x) \
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(((x) << CCSR_SSI_SFCSR_RFWM1_SHIFT) & CCSR_SSI_SFCSR_RFWM1_MASK)
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#define CCSR_SSI_SFCSR_TFWM1_SHIFT 16
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#define CCSR_SSI_SFCSR_TFWM1_MASK 0x000F0000
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#define CCSR_SSI_SFCSR_TFWM1(x) \
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(((x) << CCSR_SSI_SFCSR_TFWM1_SHIFT) & CCSR_SSI_SFCSR_TFWM1_MASK)
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#define CCSR_SSI_SFCSR_RFCNT0_SHIFT 12
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#define CCSR_SSI_SFCSR_RFCNT0_MASK 0x0000F000
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#define CCSR_SSI_SFCSR_RFCNT0(x) \
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(((x) & CCSR_SSI_SFCSR_RFCNT0_MASK) >> CCSR_SSI_SFCSR_RFCNT0_SHIFT)
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#define CCSR_SSI_SFCSR_TFCNT0_SHIFT 8
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#define CCSR_SSI_SFCSR_TFCNT0_MASK 0x00000F00
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#define CCSR_SSI_SFCSR_TFCNT0(x) \
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(((x) & CCSR_SSI_SFCSR_TFCNT0_MASK) >> CCSR_SSI_SFCSR_TFCNT0_SHIFT)
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#define CCSR_SSI_SFCSR_RFWM0_SHIFT 4
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#define CCSR_SSI_SFCSR_RFWM0_MASK 0x000000F0
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#define CCSR_SSI_SFCSR_RFWM0(x) \
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(((x) << CCSR_SSI_SFCSR_RFWM0_SHIFT) & CCSR_SSI_SFCSR_RFWM0_MASK)
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#define CCSR_SSI_SFCSR_TFWM0_SHIFT 0
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#define CCSR_SSI_SFCSR_TFWM0_MASK 0x0000000F
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#define CCSR_SSI_SFCSR_TFWM0(x) \
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(((x) << CCSR_SSI_SFCSR_TFWM0_SHIFT) & CCSR_SSI_SFCSR_TFWM0_MASK)
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#define CCSR_SSI_STR_TEST 0x00008000
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#define CCSR_SSI_STR_RCK2TCK 0x00004000
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#define CCSR_SSI_STR_RFS2TFS 0x00002000
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#define CCSR_SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F)
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#define CCSR_SSI_STR_TXD2RXD 0x00000080
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#define CCSR_SSI_STR_TCK2RCK 0x00000040
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#define CCSR_SSI_STR_TFS2RFS 0x00000020
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#define CCSR_SSI_STR_TXSTATE(x) ((x) & 0x1F)
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#define CCSR_SSI_SOR_CLKOFF 0x00000040
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#define CCSR_SSI_SOR_RX_CLR 0x00000020
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#define CCSR_SSI_SOR_TX_CLR 0x00000010
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#define CCSR_SSI_SOR_INIT 0x00000008
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#define CCSR_SSI_SOR_WAIT_SHIFT 1
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#define CCSR_SSI_SOR_WAIT_MASK 0x00000006
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#define CCSR_SSI_SOR_WAIT(x) (((x) & 3) << CCSR_SSI_SOR_WAIT_SHIFT)
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#define CCSR_SSI_SOR_SYNRST 0x00000001
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#define CCSR_SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5)
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#define CCSR_SSI_SACNT_WR 0x00000010
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#define CCSR_SSI_SACNT_RD 0x00000008
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#define CCSR_SSI_SACNT_RDWR_MASK 0x00000018
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#define CCSR_SSI_SACNT_TIF 0x00000004
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#define CCSR_SSI_SACNT_FV 0x00000002
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#define CCSR_SSI_SACNT_AC97EN 0x00000001
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#endif
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