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1419ea3b34
Make all definitions of the ColdFire Chip Select registers absolute addresses. Currently some are relative to the MBAR peripheral region. The various ColdFire parts use different methods to address the internal registers, some are absolute, some are relative to peripheral regions which can be mapped at different address ranges (such as the MBAR and IPSBAR registers). We don't want to deal with this in the code when we are accessing these registers, so make all register definitions the absolute address - factoring out whether it is an offset into a peripheral region. This makes them all consistently defined, and reduces the occasional bugs caused by inconsistent definition of the register addresses. Signed-off-by: Greg Ungerer <gerg@uclinux.org>
150 lines
6.2 KiB
C
150 lines
6.2 KiB
C
/****************************************************************************/
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/*
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* m5206sim.h -- ColdFire 5206 System Integration Module support.
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*
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* (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
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* (C) Copyright 2000, Lineo Inc. (www.lineo.com)
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*/
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/****************************************************************************/
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#ifndef m5206sim_h
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#define m5206sim_h
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/****************************************************************************/
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#define CPU_NAME "COLDFIRE(m5206)"
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#define CPU_INSTR_PER_JIFFY 3
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#define MCF_BUSCLK MCF_CLK
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#include <asm/m52xxacr.h>
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/*
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* Define the 5206 SIM register set addresses.
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*/
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#define MCFSIM_SIMR (MCF_MBAR + 0x03) /* SIM Config reg */
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#define MCFSIM_ICR1 (MCF_MBAR + 0x14) /* Intr Ctrl reg 1 */
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#define MCFSIM_ICR2 (MCF_MBAR + 0x15) /* Intr Ctrl reg 2 */
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#define MCFSIM_ICR3 (MCF_MBAR + 0x16) /* Intr Ctrl reg 3 */
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#define MCFSIM_ICR4 (MCF_MBAR + 0x17) /* Intr Ctrl reg 4 */
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#define MCFSIM_ICR5 (MCF_MBAR + 0x18) /* Intr Ctrl reg 5 */
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#define MCFSIM_ICR6 (MCF_MBAR + 0x19) /* Intr Ctrl reg 6 */
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#define MCFSIM_ICR7 (MCF_MBAR + 0x1a) /* Intr Ctrl reg 7 */
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#define MCFSIM_ICR8 (MCF_MBAR + 0x1b) /* Intr Ctrl reg 8 */
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#define MCFSIM_ICR9 (MCF_MBAR + 0x1c) /* Intr Ctrl reg 9 */
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#define MCFSIM_ICR10 (MCF_MBAR + 0x1d) /* Intr Ctrl reg 10 */
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#define MCFSIM_ICR11 (MCF_MBAR + 0x1e) /* Intr Ctrl reg 11 */
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#define MCFSIM_ICR12 (MCF_MBAR + 0x1f) /* Intr Ctrl reg 12 */
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#define MCFSIM_ICR13 (MCF_MBAR + 0x20) /* Intr Ctrl reg 13 */
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#ifdef CONFIG_M5206e
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#define MCFSIM_ICR14 (MCF_MBAR + 0x21) /* Intr Ctrl reg 14 */
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#define MCFSIM_ICR15 (MCF_MBAR + 0x22) /* Intr Ctrl reg 15 */
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#endif
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#define MCFSIM_IMR (MCF_MBAR + 0x36) /* Interrupt Mask */
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#define MCFSIM_IPR (MCF_MBAR + 0x3a) /* Interrupt Pending */
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#define MCFSIM_RSR (MCF_MBAR + 0x40) /* Reset Status */
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#define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
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#define MCFSIM_SWIVR (MCF_MBAR + 0x42) /* SW Watchdog intr */
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#define MCFSIM_SWSR (MCF_MBAR + 0x43) /* SW Watchdog srv */
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#define MCFSIM_DCRR (MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */
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#define MCFSIM_DCTR (MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
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#define MCFSIM_DAR0 (MCF_MBAR + 0x4c) /* DRAM 0 Address reg(r/w) */
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#define MCFSIM_DMR0 (MCF_MBAR + 0x50) /* DRAM 0 Mask reg (r/w) */
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#define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
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#define MCFSIM_DAR1 (MCF_MBAR + 0x58) /* DRAM 1 Address reg (r/w) */
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#define MCFSIM_DMR1 (MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */
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#define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
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#define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
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#define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
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#define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
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#define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
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#define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
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#define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
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#define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
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#define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
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#define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
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#define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
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#define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
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#define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
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#define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
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#define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
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#define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
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#define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
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#define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
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#define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
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#define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
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#define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
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#define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
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#define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
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#define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
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#define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
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#define MCFSIM_DMCR (MCF_MBAR + 0xc6) /* Default control */
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#ifdef CONFIG_M5206e
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#define MCFSIM_PAR (MCF_MBAR + 0xca) /* Pin Assignment */
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#else
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#define MCFSIM_PAR (MCF_MBAR + 0xcb) /* Pin Assignment */
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#endif
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#define MCFTIMER_BASE1 (MCF_MBAR + 0x100) /* Base of TIMER1 */
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#define MCFTIMER_BASE2 (MCF_MBAR + 0x120) /* Base of TIMER2 */
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#define MCFSIM_PADDR (MCF_MBAR + 0x1c5) /* Parallel Direction (r/w) */
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#define MCFSIM_PADAT (MCF_MBAR + 0x1c9) /* Parallel Port Value (r/w) */
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#define MCFDMA_BASE0 (MCF_MBAR + 0x200) /* Base address DMA 0 */
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#define MCFDMA_BASE1 (MCF_MBAR + 0x240) /* Base address DMA 1 */
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#if defined(CONFIG_NETtel)
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#define MCFUART_BASE0 (MCF_MBAR + 0x180) /* Base address UART0 */
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#define MCFUART_BASE1 (MCF_MBAR + 0x140) /* Base address UART1 */
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#else
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#define MCFUART_BASE0 (MCF_MBAR + 0x140) /* Base address UART0 */
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#define MCFUART_BASE1 (MCF_MBAR + 0x180) /* Base address UART1 */
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#endif
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/*
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* Define system peripheral IRQ usage.
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*/
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#define MCF_IRQ_TIMER 30 /* Timer0, Level 6 */
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#define MCF_IRQ_PROFILER 31 /* Timer1, Level 7 */
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#define MCF_IRQ_UART0 73 /* UART0 */
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#define MCF_IRQ_UART1 74 /* UART1 */
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/*
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* Generic GPIO
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*/
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#define MCFGPIO_PIN_MAX 8
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#define MCFGPIO_IRQ_VECBASE -1
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#define MCFGPIO_IRQ_MAX -1
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/*
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* Some symbol defines for the Parallel Port Pin Assignment Register
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*/
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#ifdef CONFIG_M5206e
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#define MCFSIM_PAR_DREQ0 0x100 /* Set to select DREQ0 input */
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/* Clear to select T0 input */
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#define MCFSIM_PAR_DREQ1 0x200 /* Select DREQ1 input */
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/* Clear to select T0 output */
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#endif
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/*
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* Some symbol defines for the Interrupt Control Register
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*/
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#define MCFSIM_SWDICR MCFSIM_ICR8 /* Watchdog timer ICR */
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#define MCFSIM_TIMER1ICR MCFSIM_ICR9 /* Timer 1 ICR */
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#define MCFSIM_TIMER2ICR MCFSIM_ICR10 /* Timer 2 ICR */
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#define MCFSIM_UART1ICR MCFSIM_ICR12 /* UART 1 ICR */
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#define MCFSIM_UART2ICR MCFSIM_ICR13 /* UART 2 ICR */
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#ifdef CONFIG_M5206e
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#define MCFSIM_DMA1ICR MCFSIM_ICR14 /* DMA 1 ICR */
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#define MCFSIM_DMA2ICR MCFSIM_ICR15 /* DMA 2 ICR */
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#endif
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/****************************************************************************/
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#endif /* m5206sim_h */
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