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baaece2245
Timers on Versatile Express mainboard are used as system clock/event sources. Driver assumes that they are clocked with 1MHz signal. Old V2M firmware apparently configured it by default, but on newer boards one can observe that "sleep 1" command takes over 30 seconds to finish, as the timers are fed with 32kHz instead... This patch performs required magic and also removes code clearing timer's control registers, as exactly the same operations are performed by the timer driver few jiffies later. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Tested-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
66 lines
1.6 KiB
C
66 lines
1.6 KiB
C
/*
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* arch/arm/include/asm/hardware/sp810.h
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*
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* ARM PrimeXsys System Controller SP810 header file
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*
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* Copyright (C) 2009 ST Microelectronics
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* Viresh Kumar<viresh.kumar@st.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARM_SP810_H
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#define __ASM_ARM_SP810_H
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#include <linux/io.h>
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/* sysctl registers offset */
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#define SCCTRL 0x000
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#define SCSYSSTAT 0x004
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#define SCIMCTRL 0x008
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#define SCIMSTAT 0x00C
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#define SCXTALCTRL 0x010
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#define SCPLLCTRL 0x014
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#define SCPLLFCTRL 0x018
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#define SCPERCTRL0 0x01C
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#define SCPERCTRL1 0x020
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#define SCPEREN 0x024
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#define SCPERDIS 0x028
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#define SCPERCLKEN 0x02C
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#define SCPERSTAT 0x030
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#define SCSYSID0 0xEE0
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#define SCSYSID1 0xEE4
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#define SCSYSID2 0xEE8
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#define SCSYSID3 0xEEC
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#define SCITCR 0xF00
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#define SCITIR0 0xF04
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#define SCITIR1 0xF08
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#define SCITOR 0xF0C
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#define SCCNTCTRL 0xF10
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#define SCCNTDATA 0xF14
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#define SCCNTSTEP 0xF18
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#define SCPERIPHID0 0xFE0
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#define SCPERIPHID1 0xFE4
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#define SCPERIPHID2 0xFE8
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#define SCPERIPHID3 0xFEC
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#define SCPCELLID0 0xFF0
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#define SCPCELLID1 0xFF4
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#define SCPCELLID2 0xFF8
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#define SCPCELLID3 0xFFC
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#define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15)
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#define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15)
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#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17)
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#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17)
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static inline void sysctl_soft_reset(void __iomem *base)
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{
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/* writing any value to SCSYSSTAT reg will reset system */
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writel(0, base + SCSYSSTAT);
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}
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#endif /* __ASM_ARM_SP810_H */
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