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05ad391dbc
- Ticket-based spinlock implementation and lockless lockref support - Big endian support - CPU hotplug support, currently for PSCI (Power State Coordination Interface) capable firmware - Virtual address space extended to 42-bit in the 64K page configuration (maximum VA space with 2 levels of page tables) - Compat (AArch32) kuser helpers updated to ARMv8 (make use of load-acquire/store-release instructions) - Code cleanup, defconfig update and minor fixes -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iQIcBAABAgAGBQJSfSWWAAoJEGvWsS0AyF7xSucP/i4L3C+G6Sb/esabhgulITOl 8eFZcWG3sDMciS4zL1KZPLGv5NUzjYGgXHqqguiDy0iK7bZ8zTJBk4fY0dXAuLt1 rs+ePASXVIYt96K0Lv6hejG9Qg9mepAH70ZsAFXpR8zrV70sNkgf/zEcaFY3Z8f7 JGEr4e2296lmTSQA7rLFAXf9XIOn6rf3H1z54egW4UYSHaE32NjjS6hzcXVHIHM5 pBogU9bU0L8nX6ajE6ePhhHGqgE52NuLFWIOAsz2h8UcTl6XrBxDmHmCDqJzLP2I 3GaCUUMjal/9Q6hV1ms8TRzCM877GaHlImURlUJ4zSa4EorXgJple9dbHslcdT+l WvL4Roh7iluazHFWHB93w3gTPFx8rGPzArOofqj49NCOWuWfGbQlXo31MLkRNzLy ljCKYIz5jgbkgh5REYAFY6h6G8PCPIYuiGUdc4jc15iKBgqgUDOdrZoaDcqyIXLI 7LE6xV3bruEZ2xkAFrNx961QHRKfltXHwJoeYlftQtnCJKHMB5wjoPlOShut6ALf 7fZnO0ijzRfyL6tCdw6FC/DwIgIcVBPCGNDR4JvxZ7SVR+RaJj3Flrv7plMYVoTD mmmtFOgvR7g1IcDfZY0qveTxFfhATE5wTVFktEY7Ou6Zpt7PML8gB9vegT2k4aYh 32744vX/UN17passxA1e =l5FF -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64 Pull ARM64 update from Catalin Marinas: "Main features: - Ticket-based spinlock implementation and lockless lockref support - Big endian support - CPU hotplug support, currently for PSCI (Power State Coordination Interface) capable firmware - Virtual address space extended to 42-bit in the 64K page configuration (maximum VA space with 2 levels of page tables) - Compat (AArch32) kuser helpers updated to ARMv8 (make use of load-acquire/store-release instructions) - Code cleanup, defconfig update and minor fixes" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: (43 commits) ARM64: /proc/interrupts: display IPIs of online CPUs only arm64: locks: Remove CONFIG_GENERIC_LOCKBREAK arm64: KVM: vgic: byteswap GICv2 access on world switch if BE arm64: KVM: initialize HYP mode following the kernel endianness arm64: compat: Clear the IT state independent of the 32-bit ARM or Thumb-2 mode arm64: Use 42-bit address space with 64K pages arm64: module: ensure instruction is little-endian before manipulation arm64: defconfig: Enable CONFIG_PREEMPT by default arm64: fix access to preempt_count from assembly code arm64: move enabling of GIC before CPUs are set online arm64: use generic RW_DATA_SECTION macro in linker script arm64: Slightly improve the warning on CPU0 enable-method ARM64: simplify cpu_read_bootcpu_ops using OF/DT helper ARM64: DT: define ARM64 specific arch_match_cpu_phys_id arm64: allow ioremap_cache() to use existing RAM mappings arm64: update 32-bit kuser helpers to ARMv8 arm64: perf: fix event number mask arm64: kconfig: allow CPU_BIG_ENDIAN to be selected arm64: Fix the endianness of arch_spinlock_t arm64: big-endian: write CPU holding pen address as LE ... |
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alpha | ||
arc | ||
arm | ||
arm64 | ||
avr32 | ||
blackfin | ||
c6x | ||
cris | ||
frv | ||
h8300 | ||
hexagon | ||
ia64 | ||
m32r | ||
m68k | ||
metag | ||
microblaze | ||
mips | ||
mn10300 | ||
openrisc | ||
parisc | ||
powerpc | ||
s390 | ||
score | ||
sh | ||
sparc | ||
tile | ||
um | ||
unicore32 | ||
x86 | ||
xtensa | ||
.gitignore | ||
Kconfig |