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e90ad659cd
The FIMC-LITE output DMA allows to configure different YUV order
than the order at the camera input interface. Thus there is some
limited colorspace conversion possible. This patch makes the
color format variable be per FIMC-LITE input/output, rather than
a global per device. This also fixes incorrect behavior where
color format at the FIMC-LITE.N subdev's source pad is modified
by VIDIOC_S_FMT ioctl on the related video node.
YUV order definitions are corrected so that we use notation:
| byte3 | byte2 | byte1 | byte0
-------+-------+-------+-------+------
YCBYCR | CR | Y | CB | Y
YCRYCB | CB | Y | CR | Y
CBYCRY | Y | CR | Y | CB
CRYCBY | Y | CB | Y | CR
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
151 lines
5.7 KiB
C
151 lines
5.7 KiB
C
/*
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* Copyright (C) 2012 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef FIMC_LITE_REG_H_
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#define FIMC_LITE_REG_H_
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#include "fimc-lite.h"
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/* Camera Source size */
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#define FLITE_REG_CISRCSIZE 0x00
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#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCBYCR (0 << 14)
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#define FLITE_REG_CISRCSIZE_ORDER422_IN_YCRYCB (1 << 14)
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#define FLITE_REG_CISRCSIZE_ORDER422_IN_CBYCRY (2 << 14)
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#define FLITE_REG_CISRCSIZE_ORDER422_IN_CRYCBY (3 << 14)
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#define FLITE_REG_CISRCSIZE_ORDER422_MASK (0x3 << 14)
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#define FLITE_REG_CISRCSIZE_SIZE_CAM_MASK (0x3fff << 16 | 0x3fff)
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/* Global control */
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#define FLITE_REG_CIGCTRL 0x04
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#define FLITE_REG_CIGCTRL_YUV422_1P (0x1e << 24)
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#define FLITE_REG_CIGCTRL_RAW8 (0x2a << 24)
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#define FLITE_REG_CIGCTRL_RAW10 (0x2b << 24)
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#define FLITE_REG_CIGCTRL_RAW12 (0x2c << 24)
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#define FLITE_REG_CIGCTRL_RAW14 (0x2d << 24)
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/* User defined formats. x = 0...15 */
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#define FLITE_REG_CIGCTRL_USER(x) ((0x30 + x - 1) << 24)
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#define FLITE_REG_CIGCTRL_FMT_MASK (0x3f << 24)
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#define FLITE_REG_CIGCTRL_SHADOWMASK_DISABLE (1 << 21)
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#define FLITE_REG_CIGCTRL_ODMA_DISABLE (1 << 20)
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#define FLITE_REG_CIGCTRL_SWRST_REQ (1 << 19)
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#define FLITE_REG_CIGCTRL_SWRST_RDY (1 << 18)
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#define FLITE_REG_CIGCTRL_SWRST (1 << 17)
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#define FLITE_REG_CIGCTRL_TEST_PATTERN_COLORBAR (1 << 15)
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#define FLITE_REG_CIGCTRL_INVPOLPCLK (1 << 14)
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#define FLITE_REG_CIGCTRL_INVPOLVSYNC (1 << 13)
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#define FLITE_REG_CIGCTRL_INVPOLHREF (1 << 12)
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/* Interrupts mask bits (1 disables an interrupt) */
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#define FLITE_REG_CIGCTRL_IRQ_LASTEN (1 << 8)
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#define FLITE_REG_CIGCTRL_IRQ_ENDEN (1 << 7)
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#define FLITE_REG_CIGCTRL_IRQ_STARTEN (1 << 6)
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#define FLITE_REG_CIGCTRL_IRQ_OVFEN (1 << 5)
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#define FLITE_REG_CIGCTRL_IRQ_DISABLE_MASK (0xf << 5)
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#define FLITE_REG_CIGCTRL_SELCAM_MIPI (1 << 3)
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/* Image Capture Enable */
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#define FLITE_REG_CIIMGCPT 0x08
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#define FLITE_REG_CIIMGCPT_IMGCPTEN (1 << 31)
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#define FLITE_REG_CIIMGCPT_CPT_FREN (1 << 25)
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#define FLITE_REG_CIIMGCPT_CPT_MOD_FRCNT (1 << 18)
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#define FLITE_REG_CIIMGCPT_CPT_MOD_FREN (0 << 18)
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/* Capture Sequence */
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#define FLITE_REG_CICPTSEQ 0x0c
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/* Camera Window Offset */
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#define FLITE_REG_CIWDOFST 0x10
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#define FLITE_REG_CIWDOFST_WINOFSEN (1 << 31)
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#define FLITE_REG_CIWDOFST_CLROVIY (1 << 31)
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#define FLITE_REG_CIWDOFST_CLROVFICB (1 << 15)
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#define FLITE_REG_CIWDOFST_CLROVFICR (1 << 14)
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#define FLITE_REG_CIWDOFST_OFST_MASK ((0x1fff << 16) | 0x1fff)
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/* Camera Window Offset2 */
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#define FLITE_REG_CIWDOFST2 0x14
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/* Camera Output DMA Format */
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#define FLITE_REG_CIODMAFMT 0x18
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#define FLITE_REG_CIODMAFMT_RAW_CON (1 << 15)
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#define FLITE_REG_CIODMAFMT_PACK12 (1 << 14)
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#define FLITE_REG_CIODMAFMT_YCBYCR (0 << 4)
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#define FLITE_REG_CIODMAFMT_YCRYCB (1 << 4)
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#define FLITE_REG_CIODMAFMT_CBYCRY (2 << 4)
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#define FLITE_REG_CIODMAFMT_CRYCBY (3 << 4)
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#define FLITE_REG_CIODMAFMT_YCBCR_ORDER_MASK (0x3 << 4)
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/* Camera Output Canvas */
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#define FLITE_REG_CIOCAN 0x20
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#define FLITE_REG_CIOCAN_MASK ((0x3fff << 16) | 0x3fff)
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/* Camera Output DMA Offset */
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#define FLITE_REG_CIOOFF 0x24
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#define FLITE_REG_CIOOFF_MASK ((0x3fff << 16) | 0x3fff)
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/* Camera Output DMA Start Address */
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#define FLITE_REG_CIOSA 0x30
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/* Camera Status */
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#define FLITE_REG_CISTATUS 0x40
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#define FLITE_REG_CISTATUS_MIPI_VVALID (1 << 22)
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#define FLITE_REG_CISTATUS_MIPI_HVALID (1 << 21)
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#define FLITE_REG_CISTATUS_MIPI_DVALID (1 << 20)
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#define FLITE_REG_CISTATUS_ITU_VSYNC (1 << 14)
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#define FLITE_REG_CISTATUS_ITU_HREFF (1 << 13)
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#define FLITE_REG_CISTATUS_OVFIY (1 << 10)
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#define FLITE_REG_CISTATUS_OVFICB (1 << 9)
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#define FLITE_REG_CISTATUS_OVFICR (1 << 8)
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#define FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW (1 << 7)
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#define FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND (1 << 6)
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#define FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART (1 << 5)
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#define FLITE_REG_CISTATUS_IRQ_SRC_FRMEND (1 << 4)
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#define FLITE_REG_CISTATUS_IRQ_CAM (1 << 0)
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#define FLITE_REG_CISTATUS_IRQ_MASK (0xf << 4)
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/* Camera Status2 */
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#define FLITE_REG_CISTATUS2 0x44
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#define FLITE_REG_CISTATUS2_LASTCAPEND (1 << 1)
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#define FLITE_REG_CISTATUS2_FRMEND (1 << 0)
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/* Qos Threshold */
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#define FLITE_REG_CITHOLD 0xf0
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#define FLITE_REG_CITHOLD_W_QOS_EN (1 << 30)
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/* Camera General Purpose */
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#define FLITE_REG_CIGENERAL 0xfc
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/* b0: 1 - camera B, 0 - camera A */
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#define FLITE_REG_CIGENERAL_CAM_B (1 << 0)
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/* ----------------------------------------------------------------------------
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* Function declarations
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*/
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void flite_hw_reset(struct fimc_lite *dev);
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void flite_hw_clear_pending_irq(struct fimc_lite *dev);
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u32 flite_hw_get_interrupt_source(struct fimc_lite *dev);
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void flite_hw_clear_last_capture_end(struct fimc_lite *dev);
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void flite_hw_set_interrupt_mask(struct fimc_lite *dev);
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void flite_hw_capture_start(struct fimc_lite *dev);
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void flite_hw_capture_stop(struct fimc_lite *dev);
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void flite_hw_set_camera_bus(struct fimc_lite *dev,
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struct fimc_source_info *s_info);
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void flite_hw_set_camera_polarity(struct fimc_lite *dev,
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struct fimc_source_info *cam);
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void flite_hw_set_window_offset(struct fimc_lite *dev, struct flite_frame *f);
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void flite_hw_set_source_format(struct fimc_lite *dev, struct flite_frame *f);
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void flite_hw_set_output_dma(struct fimc_lite *dev, struct flite_frame *f,
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bool enable);
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void flite_hw_set_dma_window(struct fimc_lite *dev, struct flite_frame *f);
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void flite_hw_set_test_pattern(struct fimc_lite *dev, bool on);
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void flite_hw_dump_regs(struct fimc_lite *dev, const char *label);
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static inline void flite_hw_set_output_addr(struct fimc_lite *dev, u32 paddr)
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{
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writel(paddr, dev->regs + FLITE_REG_CIOSA);
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}
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#endif /* FIMC_LITE_REG_H */
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