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This driver adds support for Last-level cache tag-and-data unit (LLC-TAD) PMU that is featured in some of the Marvell's CN10K infrastructure silicons. The LLC is divided into 2N slices distributed across N Mesh tiles in a single-socket configuration. The driver always configures the same counter for all of the TADs. The user would end up effectively reserving one of eight counters in every TAD to look across all TADs. The occurrences of events are aggregated and presented to the user at the end of an application run. The driver does not provide a way for the user to partition TADs so that different TADs are used for different applications. The event counters are zeroed to start event counting to avoid any rollover issues. TAD perf counters are 64-bit, so it's not currently possible to overflow event counters at current mesh and core frequencies. To measure tad pmu events use perf tool stat command. For instance: perf stat -e tad_dat_msh_in_dss,tad_req_msh_out_any <application> perf stat -e tad_alloc_any,tad_hit_any,tad_tag_rd <application> Signed-off-by: Bhaskara Budiredla <bbudiredla@marvell.com> Link: https://lore.kernel.org/r/20211115043506.6679-2-bbudiredla@marvell.com Signed-off-by: Will Deacon <will@kernel.org> |
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| .. | ||
| hisilicon | ||
| arm-cci.c | ||
| arm-ccn.c | ||
| arm-cmn.c | ||
| arm_dmc620_pmu.c | ||
| arm_dsu_pmu.c | ||
| arm_pmu.c | ||
| arm_pmu_acpi.c | ||
| arm_pmu_platform.c | ||
| arm_smmuv3_pmu.c | ||
| arm_spe_pmu.c | ||
| fsl_imx8_ddr_perf.c | ||
| Kconfig | ||
| Makefile | ||
| marvell_cn10k_tad_pmu.c | ||
| qcom_l2_pmu.c | ||
| qcom_l3_pmu.c | ||
| thunderx2_pmu.c | ||
| xgene_pmu.c | ||