mirror of
https://github.com/torvalds/linux
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8e02c3b782
Currently, only TLB-based ioremap() support writecombine, so add the counterpart for DMW-based ioremap() with help of DMW2. The base address (WRITECOMBINE_BASE) is configured as 0xa000000000000000. DMW3 is unused by kernel now, however firmware may leave garbage in them and interfere kernel's address mapping. So clear it as necessary. BTW, centralize the DMW configuration to macro SETUP_DMWINS. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
152 lines
3.3 KiB
ArmAsm
152 lines
3.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020-2022 Loongson Technology Corporation Limited
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*/
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#include <linux/init.h>
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#include <linux/threads.h>
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#include <asm/addrspace.h>
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#include <asm/asm.h>
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#include <asm/asmmacro.h>
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#include <asm/bug.h>
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#include <asm/regdef.h>
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#include <asm/loongarch.h>
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#include <asm/stackframe.h>
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#ifdef CONFIG_EFI_STUB
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#include "efi-header.S"
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__HEAD
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_head:
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.word MZ_MAGIC /* "MZ", MS-DOS header */
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.org 0x8
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.dword _kernel_entry /* Kernel entry point (physical address) */
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.dword _kernel_asize /* Kernel image effective size */
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.quad PHYS_LINK_KADDR /* Kernel image load offset from start of RAM */
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.org 0x38 /* 0x20 ~ 0x37 reserved */
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.long LINUX_PE_MAGIC
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.long pe_header - _head /* Offset to the PE header */
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pe_header:
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__EFI_PE_HEADER
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SYM_DATA(kernel_asize, .long _kernel_asize);
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SYM_DATA(kernel_fsize, .long _kernel_fsize);
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#endif
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__REF
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.align 12
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SYM_CODE_START(kernel_entry) # kernel entry point
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/* Config direct window and set PG */
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SETUP_DMWINS t0
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JUMP_VIRT_ADDR t0, t1
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/* Enable PG */
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li.w t0, 0xb0 # PLV=0, IE=0, PG=1
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csrwr t0, LOONGARCH_CSR_CRMD
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li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
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csrwr t0, LOONGARCH_CSR_PRMD
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li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
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csrwr t0, LOONGARCH_CSR_EUEN
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la.pcrel t0, __bss_start # clear .bss
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st.d zero, t0, 0
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la.pcrel t1, __bss_stop - LONGSIZE
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1:
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addi.d t0, t0, LONGSIZE
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st.d zero, t0, 0
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bne t0, t1, 1b
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la.pcrel t0, fw_arg0
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st.d a0, t0, 0 # firmware arguments
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la.pcrel t0, fw_arg1
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st.d a1, t0, 0
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la.pcrel t0, fw_arg2
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st.d a2, t0, 0
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#ifdef CONFIG_PAGE_SIZE_4KB
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li.d t0, 0
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li.d t1, CSR_STFILL
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csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1
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#endif
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/* KSave3 used for percpu base, initialized as 0 */
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csrwr zero, PERCPU_BASE_KS
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/* GPR21 used for percpu base (runtime), initialized as 0 */
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move u0, zero
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la.pcrel tp, init_thread_union
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/* Set the SP after an empty pt_regs. */
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PTR_LI sp, (_THREAD_SIZE - PT_SIZE)
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PTR_ADD sp, sp, tp
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set_saved_sp sp, t0, t1
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#ifdef CONFIG_RELOCATABLE
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bl relocate_kernel
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#ifdef CONFIG_RANDOMIZE_BASE
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/* Repoint the sp into the new kernel */
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PTR_LI sp, (_THREAD_SIZE - PT_SIZE)
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PTR_ADD sp, sp, tp
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set_saved_sp sp, t0, t1
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/* Jump to the new kernel: new_pc = current_pc + random_offset */
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pcaddi t0, 0
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add.d t0, t0, a0
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jirl zero, t0, 0xc
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#endif /* CONFIG_RANDOMIZE_BASE */
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#endif /* CONFIG_RELOCATABLE */
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#ifdef CONFIG_KASAN
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bl kasan_early_init
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#endif
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bl start_kernel
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ASM_BUG()
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SYM_CODE_END(kernel_entry)
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#ifdef CONFIG_SMP
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/*
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* SMP slave cpus entry point. Board specific code for bootstrap calls this
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* function after setting up the stack and tp registers.
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*/
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SYM_CODE_START(smpboot_entry)
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SETUP_DMWINS t0
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JUMP_VIRT_ADDR t0, t1
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#ifdef CONFIG_PAGE_SIZE_4KB
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li.d t0, 0
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li.d t1, CSR_STFILL
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csrxchg t0, t1, LOONGARCH_CSR_IMPCTL1
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#endif
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/* Enable PG */
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li.w t0, 0xb0 # PLV=0, IE=0, PG=1
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csrwr t0, LOONGARCH_CSR_CRMD
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li.w t0, 0x04 # PLV=0, PIE=1, PWE=0
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csrwr t0, LOONGARCH_CSR_PRMD
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li.w t0, 0x00 # FPE=0, SXE=0, ASXE=0, BTE=0
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csrwr t0, LOONGARCH_CSR_EUEN
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la.pcrel t0, cpuboot_data
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ld.d sp, t0, CPU_BOOT_STACK
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ld.d tp, t0, CPU_BOOT_TINFO
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bl start_secondary
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ASM_BUG()
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SYM_CODE_END(smpboot_entry)
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#endif /* CONFIG_SMP */
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SYM_ENTRY(kernel_entry_end, SYM_L_GLOBAL, SYM_A_NONE)
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