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https://github.com/torvalds/linux
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5c89569194
The hardware rx-filter was essentially disabled, because of a serve, yet unidentifiable problem with iwlagn. Due to these circumstances the driver and mac80211 were left with the job of filtering. This is very unfortunate and has proven to be expensive in terms of latency, memory and load. Therefore the new 1.8.8.3 firmware introduces a flexible filtering infrastructure which allows the driver to offload some of the checks (FCS & PLCP crc check, RA match, control frame filter, etc...) whenever possible. Note: This patch also includes all changes to the shared headers files since the inclusion. Signed-off-by: Christian Lamparter <chunkeey@googlemail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
565 lines
25 KiB
C
565 lines
25 KiB
C
/*
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* Shared Atheros AR9170 Header
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*
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* PHY register map
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*
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* Copyright (c) 2008-2009 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __CARL9170_SHARED_PHY_H
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#define __CARL9170_SHARED_PHY_H
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#define AR9170_PHY_REG_BASE (0x1bc000 + 0x9800)
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#define AR9170_PHY_REG(_n) (AR9170_PHY_REG_BASE + \
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((_n) << 2))
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#define AR9170_PHY_REG_TEST (AR9170_PHY_REG_BASE + 0x0000)
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#define AR9170_PHY_TEST_AGC_CLR 0x10000000
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#define AR9170_PHY_TEST_RFSILENT_BB 0x00002000
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#define AR9170_PHY_REG_TURBO (AR9170_PHY_REG_BASE + 0x0004)
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#define AR9170_PHY_TURBO_FC_TURBO_MODE 0x00000001
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#define AR9170_PHY_TURBO_FC_TURBO_SHORT 0x00000002
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#define AR9170_PHY_TURBO_FC_DYN2040_EN 0x00000004
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#define AR9170_PHY_TURBO_FC_DYN2040_PRI_ONLY 0x00000008
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#define AR9170_PHY_TURBO_FC_DYN2040_PRI_CH 0x00000010
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/* For 25 MHz channel spacing -- not used but supported by hw */
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#define AR9170_PHY_TURBO_FC_DYN2040_EXT_CH 0x00000020
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#define AR9170_PHY_TURBO_FC_HT_EN 0x00000040
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#define AR9170_PHY_TURBO_FC_SHORT_GI_40 0x00000080
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#define AR9170_PHY_TURBO_FC_WALSH 0x00000100
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#define AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1 0x00000200
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#define AR9170_PHY_TURBO_FC_ENABLE_DAC_FIFO 0x00000800
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#define AR9170_PHY_REG_TEST2 (AR9170_PHY_REG_BASE + 0x0008)
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#define AR9170_PHY_REG_TIMING2 (AR9170_PHY_REG_BASE + 0x0010)
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#define AR9170_PHY_TIMING2_USE_FORCE 0x00001000
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#define AR9170_PHY_TIMING2_FORCE 0x00000fff
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#define AR9170_PHY_TIMING2_FORCE_S 0
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#define AR9170_PHY_REG_TIMING3 (AR9170_PHY_REG_BASE + 0x0014)
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#define AR9170_PHY_TIMING3_DSC_EXP 0x0001e000
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#define AR9170_PHY_TIMING3_DSC_EXP_S 13
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#define AR9170_PHY_TIMING3_DSC_MAN 0xfffe0000
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#define AR9170_PHY_TIMING3_DSC_MAN_S 17
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#define AR9170_PHY_REG_CHIP_ID (AR9170_PHY_REG_BASE + 0x0018)
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#define AR9170_PHY_CHIP_ID_REV_0 0x80
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#define AR9170_PHY_CHIP_ID_REV_1 0x81
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#define AR9170_PHY_CHIP_ID_9160_REV_0 0xb0
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#define AR9170_PHY_REG_ACTIVE (AR9170_PHY_REG_BASE + 0x001c)
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#define AR9170_PHY_ACTIVE_EN 0x00000001
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#define AR9170_PHY_ACTIVE_DIS 0x00000000
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#define AR9170_PHY_REG_RF_CTL2 (AR9170_PHY_REG_BASE + 0x0024)
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#define AR9170_PHY_RF_CTL2_TX_END_DATA_START 0x000000ff
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#define AR9170_PHY_RF_CTL2_TX_END_DATA_START_S 0
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#define AR9170_PHY_RF_CTL2_TX_END_PA_ON 0x0000ff00
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#define AR9170_PHY_RF_CTL2_TX_END_PA_ON_S 8
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#define AR9170_PHY_REG_RF_CTL3 (AR9170_PHY_REG_BASE + 0x0028)
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#define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON 0x00ff0000
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#define AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON_S 16
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#define AR9170_PHY_REG_ADC_CTL (AR9170_PHY_REG_BASE + 0x002c)
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#define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN 0x00000003
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#define AR9170_PHY_ADC_CTL_OFF_INBUFGAIN_S 0
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#define AR9170_PHY_ADC_CTL_OFF_PWDDAC 0x00002000
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#define AR9170_PHY_ADC_CTL_OFF_PWDBANDGAP 0x00004000
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#define AR9170_PHY_ADC_CTL_OFF_PWDADC 0x00008000
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#define AR9170_PHY_ADC_CTL_ON_INBUFGAIN 0x00030000
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#define AR9170_PHY_ADC_CTL_ON_INBUFGAIN_S 16
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#define AR9170_PHY_REG_ADC_SERIAL_CTL (AR9170_PHY_REG_BASE + 0x0030)
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#define AR9170_PHY_ADC_SCTL_SEL_INTERNAL_ADDAC 0x00000000
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#define AR9170_PHY_ADC_SCTL_SEL_EXTERNAL_RADIO 0x00000001
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#define AR9170_PHY_REG_RF_CTL4 (AR9170_PHY_REG_BASE + 0x0034)
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#define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF 0xff000000
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#define AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF_S 24
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#define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF 0x00ff0000
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#define AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF_S 16
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#define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON 0x0000ff00
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#define AR9170_PHY_RF_CTL4_FRAME_XPAB_ON_S 8
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#define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON 0x000000ff
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#define AR9170_PHY_RF_CTL4_FRAME_XPAA_ON_S 0
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#define AR9170_PHY_REG_TSTDAC_CONST (AR9170_PHY_REG_BASE + 0x003c)
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#define AR9170_PHY_REG_SETTLING (AR9170_PHY_REG_BASE + 0x0044)
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#define AR9170_PHY_SETTLING_SWITCH 0x00003f80
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#define AR9170_PHY_SETTLING_SWITCH_S 7
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#define AR9170_PHY_REG_RXGAIN (AR9170_PHY_REG_BASE + 0x0048)
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#define AR9170_PHY_REG_RXGAIN_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2048)
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#define AR9170_PHY_RXGAIN_TXRX_ATTEN 0x0003f000
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#define AR9170_PHY_RXGAIN_TXRX_ATTEN_S 12
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#define AR9170_PHY_RXGAIN_TXRX_RF_MAX 0x007c0000
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#define AR9170_PHY_RXGAIN_TXRX_RF_MAX_S 18
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#define AR9170_PHY_REG_DESIRED_SZ (AR9170_PHY_REG_BASE + 0x0050)
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#define AR9170_PHY_DESIRED_SZ_ADC 0x000000ff
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#define AR9170_PHY_DESIRED_SZ_ADC_S 0
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#define AR9170_PHY_DESIRED_SZ_PGA 0x0000ff00
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#define AR9170_PHY_DESIRED_SZ_PGA_S 8
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#define AR9170_PHY_DESIRED_SZ_TOT_DES 0x0ff00000
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#define AR9170_PHY_DESIRED_SZ_TOT_DES_S 20
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#define AR9170_PHY_REG_FIND_SIG (AR9170_PHY_REG_BASE + 0x0058)
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#define AR9170_PHY_FIND_SIG_FIRSTEP 0x0003f000
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#define AR9170_PHY_FIND_SIG_FIRSTEP_S 12
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#define AR9170_PHY_FIND_SIG_FIRPWR 0x03fc0000
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#define AR9170_PHY_FIND_SIG_FIRPWR_S 18
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#define AR9170_PHY_REG_AGC_CTL1 (AR9170_PHY_REG_BASE + 0x005c)
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#define AR9170_PHY_AGC_CTL1_COARSE_LOW 0x00007f80
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#define AR9170_PHY_AGC_CTL1_COARSE_LOW_S 7
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#define AR9170_PHY_AGC_CTL1_COARSE_HIGH 0x003f8000
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#define AR9170_PHY_AGC_CTL1_COARSE_HIGH_S 15
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#define AR9170_PHY_REG_AGC_CONTROL (AR9170_PHY_REG_BASE + 0x0060)
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#define AR9170_PHY_AGC_CONTROL_CAL 0x00000001
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#define AR9170_PHY_AGC_CONTROL_NF 0x00000002
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#define AR9170_PHY_AGC_CONTROL_ENABLE_NF 0x00008000
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#define AR9170_PHY_AGC_CONTROL_FLTR_CAL 0x00010000
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#define AR9170_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000
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#define AR9170_PHY_REG_CCA (AR9170_PHY_REG_BASE + 0x0064)
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#define AR9170_PHY_CCA_MINCCA_PWR 0x0ff80000
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#define AR9170_PHY_CCA_MINCCA_PWR_S 19
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#define AR9170_PHY_CCA_THRESH62 0x0007f000
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#define AR9170_PHY_CCA_THRESH62_S 12
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#define AR9170_PHY_REG_SFCORR (AR9170_PHY_REG_BASE + 0x0068)
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#define AR9170_PHY_SFCORR_M2COUNT_THR 0x0000001f
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#define AR9170_PHY_SFCORR_M2COUNT_THR_S 0
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#define AR9170_PHY_SFCORR_M1_THRESH 0x00fe0000
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#define AR9170_PHY_SFCORR_M1_THRESH_S 17
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#define AR9170_PHY_SFCORR_M2_THRESH 0x7f000000
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#define AR9170_PHY_SFCORR_M2_THRESH_S 24
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#define AR9170_PHY_REG_SFCORR_LOW (AR9170_PHY_REG_BASE + 0x006c)
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#define AR9170_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
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#define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003f00
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#define AR9170_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S 8
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#define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001fc000
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#define AR9170_PHY_SFCORR_LOW_M1_THRESH_LOW_S 14
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#define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0fe00000
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#define AR9170_PHY_SFCORR_LOW_M2_THRESH_LOW_S 21
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#define AR9170_PHY_REG_SLEEP_CTR_CONTROL (AR9170_PHY_REG_BASE + 0x0070)
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#define AR9170_PHY_REG_SLEEP_CTR_LIMIT (AR9170_PHY_REG_BASE + 0x0074)
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#define AR9170_PHY_REG_SLEEP_SCAL (AR9170_PHY_REG_BASE + 0x0078)
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#define AR9170_PHY_REG_PLL_CTL (AR9170_PHY_REG_BASE + 0x007c)
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#define AR9170_PHY_PLL_CTL_40 0xaa
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#define AR9170_PHY_PLL_CTL_40_5413 0x04
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#define AR9170_PHY_PLL_CTL_44 0xab
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#define AR9170_PHY_PLL_CTL_44_2133 0xeb
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#define AR9170_PHY_PLL_CTL_40_2133 0xea
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#define AR9170_PHY_REG_BIN_MASK_1 (AR9170_PHY_REG_BASE + 0x0100)
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#define AR9170_PHY_REG_BIN_MASK_2 (AR9170_PHY_REG_BASE + 0x0104)
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#define AR9170_PHY_REG_BIN_MASK_3 (AR9170_PHY_REG_BASE + 0x0108)
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#define AR9170_PHY_REG_MASK_CTL (AR9170_PHY_REG_BASE + 0x010c)
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/* analogue power on time (100ns) */
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#define AR9170_PHY_REG_RX_DELAY (AR9170_PHY_REG_BASE + 0x0114)
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#define AR9170_PHY_REG_SEARCH_START_DELAY (AR9170_PHY_REG_BASE + 0x0118)
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#define AR9170_PHY_RX_DELAY_DELAY 0x00003fff
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#define AR9170_PHY_REG_TIMING_CTRL4(_i) (AR9170_PHY_REG_BASE + \
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(0x0120 + ((_i) << 12)))
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#define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF 0x01f
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#define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF_S 0
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#define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF 0x7e0
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#define AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF_S 5
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#define AR9170_PHY_TIMING_CTRL4_IQCORR_ENABLE 0x800
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#define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX 0xf000
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#define AR9170_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX_S 12
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#define AR9170_PHY_TIMING_CTRL4_DO_IQCAL 0x10000
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#define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI 0x80000000
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#define AR9170_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER 0x40000000
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#define AR9170_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK 0x20000000
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#define AR9170_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK 0x10000000
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#define AR9170_PHY_REG_TIMING5 (AR9170_PHY_REG_BASE + 0x0124)
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#define AR9170_PHY_TIMING5_CYCPWR_THR1 0x000000fe
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#define AR9170_PHY_TIMING5_CYCPWR_THR1_S 1
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#define AR9170_PHY_REG_POWER_TX_RATE1 (AR9170_PHY_REG_BASE + 0x0134)
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#define AR9170_PHY_REG_POWER_TX_RATE2 (AR9170_PHY_REG_BASE + 0x0138)
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#define AR9170_PHY_REG_POWER_TX_RATE_MAX (AR9170_PHY_REG_BASE + 0x013c)
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#define AR9170_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
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#define AR9170_PHY_REG_FRAME_CTL (AR9170_PHY_REG_BASE + 0x0144)
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#define AR9170_PHY_FRAME_CTL_TX_CLIP 0x00000038
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#define AR9170_PHY_FRAME_CTL_TX_CLIP_S 3
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#define AR9170_PHY_REG_SPUR_REG (AR9170_PHY_REG_BASE + 0x014c)
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#define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL (0xff << 18)
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#define AR9170_PHY_SPUR_REG_MASK_RATE_CNTL_S 18
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#define AR9170_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000
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#define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT (0xff << 9)
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#define AR9170_PHY_SPUR_REG_MASK_RATE_SELECT_S 9
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#define AR9170_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI 0x100
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#define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x7f
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#define AR9170_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
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#define AR9170_PHY_REG_RADAR_EXT (AR9170_PHY_REG_BASE + 0x0140)
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#define AR9170_PHY_RADAR_EXT_ENA 0x00004000
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#define AR9170_PHY_REG_RADAR_0 (AR9170_PHY_REG_BASE + 0x0154)
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#define AR9170_PHY_RADAR_0_ENA 0x00000001
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#define AR9170_PHY_RADAR_0_FFT_ENA 0x80000000
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/* inband pulse threshold */
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#define AR9170_PHY_RADAR_0_INBAND 0x0000003e
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#define AR9170_PHY_RADAR_0_INBAND_S 1
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/* pulse RSSI threshold */
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#define AR9170_PHY_RADAR_0_PRSSI 0x00000fc0
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#define AR9170_PHY_RADAR_0_PRSSI_S 6
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/* pulse height threshold */
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#define AR9170_PHY_RADAR_0_HEIGHT 0x0003f000
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#define AR9170_PHY_RADAR_0_HEIGHT_S 12
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/* radar RSSI threshold */
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#define AR9170_PHY_RADAR_0_RRSSI 0x00fc0000
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#define AR9170_PHY_RADAR_0_RRSSI_S 18
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/* radar firepower threshold */
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#define AR9170_PHY_RADAR_0_FIRPWR 0x7f000000
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#define AR9170_PHY_RADAR_0_FIRPWR_S 24
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#define AR9170_PHY_REG_RADAR_1 (AR9170_PHY_REG_BASE + 0x0158)
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#define AR9170_PHY_RADAR_1_RELPWR_ENA 0x00800000
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#define AR9170_PHY_RADAR_1_USE_FIR128 0x00400000
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#define AR9170_PHY_RADAR_1_RELPWR_THRESH 0x003f0000
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#define AR9170_PHY_RADAR_1_RELPWR_THRESH_S 16
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#define AR9170_PHY_RADAR_1_BLOCK_CHECK 0x00008000
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#define AR9170_PHY_RADAR_1_MAX_RRSSI 0x00004000
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#define AR9170_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
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#define AR9170_PHY_RADAR_1_RELSTEP_THRESH 0x00001f00
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#define AR9170_PHY_RADAR_1_RELSTEP_THRESH_S 8
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#define AR9170_PHY_RADAR_1_MAXLEN 0x000000ff
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#define AR9170_PHY_RADAR_1_MAXLEN_S 0
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#define AR9170_PHY_REG_SWITCH_CHAIN_0 (AR9170_PHY_REG_BASE + 0x0160)
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#define AR9170_PHY_REG_SWITCH_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2160)
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#define AR9170_PHY_REG_SWITCH_COM (AR9170_PHY_REG_BASE + 0x0164)
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#define AR9170_PHY_REG_CCA_THRESHOLD (AR9170_PHY_REG_BASE + 0x0168)
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#define AR9170_PHY_REG_SIGMA_DELTA (AR9170_PHY_REG_BASE + 0x016c)
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#define AR9170_PHY_SIGMA_DELTA_ADC_SEL 0x00000003
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#define AR9170_PHY_SIGMA_DELTA_ADC_SEL_S 0
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#define AR9170_PHY_SIGMA_DELTA_FILT2 0x000000f8
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#define AR9170_PHY_SIGMA_DELTA_FILT2_S 3
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#define AR9170_PHY_SIGMA_DELTA_FILT1 0x00001f00
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#define AR9170_PHY_SIGMA_DELTA_FILT1_S 8
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#define AR9170_PHY_SIGMA_DELTA_ADC_CLIP 0x01ffe000
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#define AR9170_PHY_SIGMA_DELTA_ADC_CLIP_S 13
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#define AR9170_PHY_REG_RESTART (AR9170_PHY_REG_BASE + 0x0170)
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#define AR9170_PHY_RESTART_DIV_GC 0x001c0000
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#define AR9170_PHY_RESTART_DIV_GC_S 18
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#define AR9170_PHY_REG_RFBUS_REQ (AR9170_PHY_REG_BASE + 0x017c)
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#define AR9170_PHY_RFBUS_REQ_EN 0x00000001
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#define AR9170_PHY_REG_TIMING7 (AR9170_PHY_REG_BASE + 0x0180)
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#define AR9170_PHY_REG_TIMING8 (AR9170_PHY_REG_BASE + 0x0184)
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#define AR9170_PHY_TIMING8_PILOT_MASK_2 0x000fffff
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#define AR9170_PHY_TIMING8_PILOT_MASK_2_S 0
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#define AR9170_PHY_REG_BIN_MASK2_1 (AR9170_PHY_REG_BASE + 0x0188)
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#define AR9170_PHY_REG_BIN_MASK2_2 (AR9170_PHY_REG_BASE + 0x018c)
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#define AR9170_PHY_REG_BIN_MASK2_3 (AR9170_PHY_REG_BASE + 0x0190)
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#define AR9170_PHY_REG_BIN_MASK2_4 (AR9170_PHY_REG_BASE + 0x0194)
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#define AR9170_PHY_BIN_MASK2_4_MASK_4 0x00003fff
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#define AR9170_PHY_BIN_MASK2_4_MASK_4_S 0
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#define AR9170_PHY_REG_TIMING9 (AR9170_PHY_REG_BASE + 0x0198)
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#define AR9170_PHY_REG_TIMING10 (AR9170_PHY_REG_BASE + 0x019c)
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#define AR9170_PHY_TIMING10_PILOT_MASK_2 0x000fffff
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#define AR9170_PHY_TIMING10_PILOT_MASK_2_S 0
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#define AR9170_PHY_REG_TIMING11 (AR9170_PHY_REG_BASE + 0x01a0)
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#define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE 0x000fffff
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#define AR9170_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
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#define AR9170_PHY_TIMING11_SPUR_FREQ_SD 0x3ff00000
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#define AR9170_PHY_TIMING11_SPUR_FREQ_SD_S 20
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#define AR9170_PHY_TIMING11_USE_SPUR_IN_AGC 0x40000000
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#define AR9170_PHY_TIMING11_USE_SPUR_IN_SELFCOR 0x80000000
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#define AR9170_PHY_REG_RX_CHAINMASK (AR9170_PHY_REG_BASE + 0x01a4)
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#define AR9170_PHY_REG_NEW_ADC_DC_GAIN_CORR(_i) (AR9170_PHY_REG_BASE + \
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0x01b4 + ((_i) << 12))
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#define AR9170_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
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#define AR9170_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
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#define AR9170_PHY_REG_MULTICHAIN_GAIN_CTL (AR9170_PHY_REG_BASE + 0x01ac)
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#define AR9170_PHY_9285_ANT_DIV_CTL_ALL 0x7f000000
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#define AR9170_PHY_9285_ANT_DIV_CTL 0x01000000
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#define AR9170_PHY_9285_ANT_DIV_CTL_S 24
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#define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF 0x06000000
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#define AR9170_PHY_9285_ANT_DIV_ALT_LNACONF_S 25
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#define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF 0x18000000
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#define AR9170_PHY_9285_ANT_DIV_MAIN_LNACONF_S 27
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#define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB 0x20000000
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#define AR9170_PHY_9285_ANT_DIV_ALT_GAINTB_S 29
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#define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB 0x40000000
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#define AR9170_PHY_9285_ANT_DIV_MAIN_GAINTB_S 30
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#define AR9170_PHY_9285_ANT_DIV_LNA1 2
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#define AR9170_PHY_9285_ANT_DIV_LNA2 1
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#define AR9170_PHY_9285_ANT_DIV_LNA1_PLUS_LNA2 3
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#define AR9170_PHY_9285_ANT_DIV_LNA1_MINUS_LNA2 0
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#define AR9170_PHY_9285_ANT_DIV_GAINTB_0 0
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#define AR9170_PHY_9285_ANT_DIV_GAINTB_1 1
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#define AR9170_PHY_REG_EXT_CCA0 (AR9170_PHY_REG_BASE + 0x01b8)
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#define AR9170_PHY_REG_EXT_CCA0_THRESH62 0x000000ff
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#define AR9170_PHY_REG_EXT_CCA0_THRESH62_S 0
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#define AR9170_PHY_REG_EXT_CCA (AR9170_PHY_REG_BASE + 0x01bc)
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#define AR9170_PHY_EXT_CCA_CYCPWR_THR1 0x0000fe00
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#define AR9170_PHY_EXT_CCA_CYCPWR_THR1_S 9
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#define AR9170_PHY_EXT_CCA_THRESH62 0x007f0000
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#define AR9170_PHY_EXT_CCA_THRESH62_S 16
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#define AR9170_PHY_EXT_MINCCA_PWR 0xff800000
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#define AR9170_PHY_EXT_MINCCA_PWR_S 23
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#define AR9170_PHY_REG_SFCORR_EXT (AR9170_PHY_REG_BASE + 0x01c0)
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#define AR9170_PHY_SFCORR_EXT_M1_THRESH 0x0000007f
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#define AR9170_PHY_SFCORR_EXT_M1_THRESH_S 0
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#define AR9170_PHY_SFCORR_EXT_M2_THRESH 0x00003f80
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#define AR9170_PHY_SFCORR_EXT_M2_THRESH_S 7
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#define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001fc000
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#define AR9170_PHY_SFCORR_EXT_M1_THRESH_LOW_S 14
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#define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0fe00000
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#define AR9170_PHY_SFCORR_EXT_M2_THRESH_LOW_S 21
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#define AR9170_PHY_SFCORR_SPUR_SUBCHNL_SD_S 28
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#define AR9170_PHY_REG_HALFGI (AR9170_PHY_REG_BASE + 0x01d0)
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#define AR9170_PHY_HALFGI_DSC_MAN 0x0007fff0
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#define AR9170_PHY_HALFGI_DSC_MAN_S 4
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#define AR9170_PHY_HALFGI_DSC_EXP 0x0000000f
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#define AR9170_PHY_HALFGI_DSC_EXP_S 0
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#define AR9170_PHY_REG_CHANNEL_MASK_01_30 (AR9170_PHY_REG_BASE + 0x01d4)
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#define AR9170_PHY_REG_CHANNEL_MASK_31_60 (AR9170_PHY_REG_BASE + 0x01d8)
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#define AR9170_PHY_REG_CHAN_INFO_MEMORY (AR9170_PHY_REG_BASE + 0x01dc)
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#define AR9170_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
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#define AR9170_PHY_REG_HEAVY_CLIP_ENABLE (AR9170_PHY_REG_BASE + 0x01e0)
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#define AR9170_PHY_REG_HEAVY_CLIP_FACTOR_RIFS (AR9170_PHY_REG_BASE + 0x01ec)
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#define AR9170_PHY_RIFS_INIT_DELAY 0x03ff0000
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#define AR9170_PHY_REG_CALMODE (AR9170_PHY_REG_BASE + 0x01f0)
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#define AR9170_PHY_CALMODE_IQ 0x00000000
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#define AR9170_PHY_CALMODE_ADC_GAIN 0x00000001
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#define AR9170_PHY_CALMODE_ADC_DC_PER 0x00000002
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#define AR9170_PHY_CALMODE_ADC_DC_INIT 0x00000003
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#define AR9170_PHY_REG_REFCLKDLY (AR9170_PHY_REG_BASE + 0x01f4)
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#define AR9170_PHY_REG_REFCLKPD (AR9170_PHY_REG_BASE + 0x01f8)
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#define AR9170_PHY_REG_CAL_MEAS_0(_i) (AR9170_PHY_REG_BASE + \
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0x0410 + ((_i) << 12))
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#define AR9170_PHY_REG_CAL_MEAS_1(_i) (AR9170_PHY_REG_BASE + \
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0x0414 \ + ((_i) << 12))
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#define AR9170_PHY_REG_CAL_MEAS_2(_i) (AR9170_PHY_REG_BASE + \
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0x0418 + ((_i) << 12))
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#define AR9170_PHY_REG_CAL_MEAS_3(_i) (AR9170_PHY_REG_BASE + \
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0x041c + ((_i) << 12))
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#define AR9170_PHY_REG_CURRENT_RSSI (AR9170_PHY_REG_BASE + 0x041c)
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#define AR9170_PHY_REG_RFBUS_GRANT (AR9170_PHY_REG_BASE + 0x0420)
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#define AR9170_PHY_RFBUS_GRANT_EN 0x00000001
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#define AR9170_PHY_REG_CHAN_INFO_GAIN_DIFF (AR9170_PHY_REG_BASE + 0x04f4)
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#define AR9170_PHY_CHAN_INFO_GAIN_DIFF_UPPER_LIMIT 320
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#define AR9170_PHY_REG_CHAN_INFO_GAIN (AR9170_PHY_REG_BASE + 0x04fc)
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#define AR9170_PHY_REG_MODE (AR9170_PHY_REG_BASE + 0x0a00)
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#define AR9170_PHY_MODE_ASYNCFIFO 0x80
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#define AR9170_PHY_MODE_AR2133 0x08
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#define AR9170_PHY_MODE_AR5111 0x00
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#define AR9170_PHY_MODE_AR5112 0x08
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#define AR9170_PHY_MODE_DYNAMIC 0x04
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#define AR9170_PHY_MODE_RF2GHZ 0x02
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#define AR9170_PHY_MODE_RF5GHZ 0x00
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#define AR9170_PHY_MODE_CCK 0x01
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#define AR9170_PHY_MODE_OFDM 0x00
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#define AR9170_PHY_MODE_DYN_CCK_DISABLE 0x100
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#define AR9170_PHY_REG_CCK_TX_CTRL (AR9170_PHY_REG_BASE + 0x0a04)
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#define AR9170_PHY_CCK_TX_CTRL_JAPAN 0x00000010
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#define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK 0x0000000c
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#define AR9170_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK_S 2
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#define AR9170_PHY_REG_CCK_DETECT (AR9170_PHY_REG_BASE + 0x0a08)
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#define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003f
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#define AR9170_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
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/* [12:6] settling time for antenna switch */
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#define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001fc0
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#define AR9170_PHY_CCK_DETECT_ANT_SWITCH_TIME_S 6
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#define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
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#define AR9170_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV_S 13
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#define AR9170_PHY_REG_GAIN_2GHZ (AR9170_PHY_REG_BASE + 0x0a0c)
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#define AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2 (AR9170_PHY_REG_BASE + 0x2a0c)
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#define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN 0x00fc0000
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#define AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN_S 18
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#define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN 0x00003c00
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#define AR9170_PHY_GAIN_2GHZ_BSW_MARGIN_S 10
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#define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001f
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#define AR9170_PHY_GAIN_2GHZ_BSW_ATTEN_S 0
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#define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003e0000
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#define AR9170_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17
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#define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001f000
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#define AR9170_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12
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#define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000fc0
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#define AR9170_PHY_GAIN_2GHZ_XATTEN2_DB_S 6
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#define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003f
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#define AR9170_PHY_GAIN_2GHZ_XATTEN1_DB_S 0
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#define AR9170_PHY_REG_CCK_RXCTRL4 (AR9170_PHY_REG_BASE + 0x0a1c)
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#define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT 0x01f80000
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#define AR9170_PHY_CCK_RXCTRL4_FREQ_EST_SHORT_S 19
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#define AR9170_PHY_REG_DAG_CTRLCCK (AR9170_PHY_REG_BASE + 0x0a28)
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#define AR9170_REG_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
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#define AR9170_REG_DAG_CTRLCCK_RSSI_THR 0x0001fc00
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#define AR9170_REG_DAG_CTRLCCK_RSSI_THR_S 10
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#define AR9170_PHY_REG_FORCE_CLKEN_CCK (AR9170_PHY_REG_BASE + 0x0a2c)
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#define AR9170_FORCE_CLKEN_CCK_MRC_MUX 0x00000040
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#define AR9170_PHY_REG_POWER_TX_RATE3 (AR9170_PHY_REG_BASE + 0x0a34)
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#define AR9170_PHY_REG_POWER_TX_RATE4 (AR9170_PHY_REG_BASE + 0x0a38)
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#define AR9170_PHY_REG_SCRM_SEQ_XR (AR9170_PHY_REG_BASE + 0x0a3c)
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#define AR9170_PHY_REG_HEADER_DETECT_XR (AR9170_PHY_REG_BASE + 0x0a40)
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#define AR9170_PHY_REG_CHIRP_DETECTED_XR (AR9170_PHY_REG_BASE + 0x0a44)
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#define AR9170_PHY_REG_BLUETOOTH (AR9170_PHY_REG_BASE + 0x0a54)
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#define AR9170_PHY_REG_TPCRG1 (AR9170_PHY_REG_BASE + 0x0a58)
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#define AR9170_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
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#define AR9170_PHY_TPCRG1_NUM_PD_GAIN_S 14
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#define AR9170_PHY_TPCRG1_PD_GAIN_1 0x00030000
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#define AR9170_PHY_TPCRG1_PD_GAIN_1_S 16
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#define AR9170_PHY_TPCRG1_PD_GAIN_2 0x000c0000
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#define AR9170_PHY_TPCRG1_PD_GAIN_2_S 18
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#define AR9170_PHY_TPCRG1_PD_GAIN_3 0x00300000
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#define AR9170_PHY_TPCRG1_PD_GAIN_3_S 20
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#define AR9170_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
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#define AR9170_PHY_TPCRG1_PD_CAL_ENABLE_S 22
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#define AR9170_PHY_REG_TX_PWRCTRL4 (AR9170_PHY_REG_BASE + 0x0a64)
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#define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID 0x00000001
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#define AR9170_PHY_TX_PWRCTRL_PD_AVG_VALID_S 0
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#define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT 0x000001fe
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#define AR9170_PHY_TX_PWRCTRL_PD_AVG_OUT_S 1
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#define AR9170_PHY_REG_ANALOG_SWAP (AR9170_PHY_REG_BASE + 0x0a68)
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#define AR9170_PHY_ANALOG_SWAP_AB 0x0001
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#define AR9170_PHY_ANALOG_SWAP_ALT_CHAIN 0x00000040
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#define AR9170_PHY_REG_TPCRG5 (AR9170_PHY_REG_BASE + 0x0a6c)
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#define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000f
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#define AR9170_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
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#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003f0
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#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_1_S 4
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#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000fc00
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#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_2_S 10
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#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003f0000
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#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_3_S 16
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#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0fc00000
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#define AR9170_PHY_TPCRG5_PD_GAIN_BOUNDARY_4_S 22
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#define AR9170_PHY_REG_TX_PWRCTRL6_0 (AR9170_PHY_REG_BASE + 0x0a70)
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#define AR9170_PHY_REG_TX_PWRCTRL6_1 (AR9170_PHY_REG_BASE + 0x1a70)
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#define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE 0x03000000
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#define AR9170_PHY_TX_PWRCTRL_ERR_EST_MODE_S 24
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#define AR9170_PHY_REG_TX_PWRCTRL7 (AR9170_PHY_REG_BASE + 0x0a74)
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#define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN 0x01f80000
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#define AR9170_PHY_TX_PWRCTRL_INIT_TX_GAIN_S 19
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#define AR9170_PHY_REG_TX_PWRCTRL9 (AR9170_PHY_REG_BASE + 0x0a7c)
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#define AR9170_PHY_TX_DESIRED_SCALE_CCK 0x00007c00
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#define AR9170_PHY_TX_DESIRED_SCALE_CCK_S 10
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#define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL 0x80000000
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#define AR9170_PHY_TX_PWRCTRL9_RES_DC_REMOVAL_S 31
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#define AR9170_PHY_REG_TX_GAIN_TBL1 (AR9170_PHY_REG_BASE + 0x0b00)
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#define AR9170_PHY_TX_GAIN 0x0007f000
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#define AR9170_PHY_TX_GAIN_S 12
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/* Carrier leak calibration control, do it after AGC calibration */
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#define AR9170_PHY_REG_CL_CAL_CTL (AR9170_PHY_REG_BASE + 0x0b58)
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#define AR9170_PHY_CL_CAL_ENABLE 0x00000002
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#define AR9170_PHY_CL_CAL_PARALLEL_CAL_ENABLE 0x00000001
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#define AR9170_PHY_REG_POWER_TX_RATE5 (AR9170_PHY_REG_BASE + 0x0b8c)
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#define AR9170_PHY_REG_POWER_TX_RATE6 (AR9170_PHY_REG_BASE + 0x0b90)
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#define AR9170_PHY_REG_CH0_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x0b98)
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#define AR9170_PHY_REG_CH1_TX_PWRCTRL11 (AR9170_PHY_REG_BASE + 0x1b98)
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#define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP 0x0000fc00
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#define AR9170_PHY_TX_CHX_PWRCTRL_OLPC_TEMP_COMP_S 10
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#define AR9170_PHY_REG_CAL_CHAINMASK (AR9170_PHY_REG_BASE + 0x0b9c)
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#define AR9170_PHY_REG_VIT_MASK2_M_46_61 (AR9170_PHY_REG_BASE + 0x0ba0)
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#define AR9170_PHY_REG_MASK2_M_31_45 (AR9170_PHY_REG_BASE + 0x0ba4)
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#define AR9170_PHY_REG_MASK2_M_16_30 (AR9170_PHY_REG_BASE + 0x0ba8)
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#define AR9170_PHY_REG_MASK2_M_00_15 (AR9170_PHY_REG_BASE + 0x0bac)
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#define AR9170_PHY_REG_PILOT_MASK_01_30 (AR9170_PHY_REG_BASE + 0x0bb0)
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#define AR9170_PHY_REG_PILOT_MASK_31_60 (AR9170_PHY_REG_BASE + 0x0bb4)
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#define AR9170_PHY_REG_MASK2_P_15_01 (AR9170_PHY_REG_BASE + 0x0bb8)
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#define AR9170_PHY_REG_MASK2_P_30_16 (AR9170_PHY_REG_BASE + 0x0bbc)
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#define AR9170_PHY_REG_MASK2_P_45_31 (AR9170_PHY_REG_BASE + 0x0bc0)
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#define AR9170_PHY_REG_MASK2_P_61_45 (AR9170_PHY_REG_BASE + 0x0bc4)
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#define AR9170_PHY_REG_POWER_TX_SUB (AR9170_PHY_REG_BASE + 0x0bc8)
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#define AR9170_PHY_REG_POWER_TX_RATE7 (AR9170_PHY_REG_BASE + 0x0bcc)
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#define AR9170_PHY_REG_POWER_TX_RATE8 (AR9170_PHY_REG_BASE + 0x0bd0)
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#define AR9170_PHY_REG_POWER_TX_RATE9 (AR9170_PHY_REG_BASE + 0x0bd4)
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#define AR9170_PHY_REG_XPA_CFG (AR9170_PHY_REG_BASE + 0x0bd8)
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#define AR9170_PHY_FORCE_XPA_CFG 0x000000001
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#define AR9170_PHY_FORCE_XPA_CFG_S 0
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|
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#define AR9170_PHY_REG_CH1_CCA (AR9170_PHY_REG_BASE + 0x1064)
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#define AR9170_PHY_CH1_MINCCA_PWR 0x0ff80000
|
|
#define AR9170_PHY_CH1_MINCCA_PWR_S 19
|
|
|
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#define AR9170_PHY_REG_CH2_CCA (AR9170_PHY_REG_BASE + 0x2064)
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#define AR9170_PHY_CH2_MINCCA_PWR 0x0ff80000
|
|
#define AR9170_PHY_CH2_MINCCA_PWR_S 19
|
|
|
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#define AR9170_PHY_REG_CH1_EXT_CCA (AR9170_PHY_REG_BASE + 0x11bc)
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#define AR9170_PHY_CH1_EXT_MINCCA_PWR 0xff800000
|
|
#define AR9170_PHY_CH1_EXT_MINCCA_PWR_S 23
|
|
|
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#define AR9170_PHY_REG_CH2_EXT_CCA (AR9170_PHY_REG_BASE + 0x21bc)
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#define AR9170_PHY_CH2_EXT_MINCCA_PWR 0xff800000
|
|
#define AR9170_PHY_CH2_EXT_MINCCA_PWR_S 23
|
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|
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#endif /* __CARL9170_SHARED_PHY_H */
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