Commit graph

17 commits

Author SHA1 Message Date
Mike Frysinger a055b2b4de Blackfin arch: remove useless CONFIG_IRQCHIP_DEMUX_GPIO
since we have this always turned on now and dont want it off (and hasnt been an option in a while)

Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-11-15 21:12:32 +08:00
Michael Hennerich 4fb4524162 Blackfin arch: Optimization - no need to make additional math here
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-10-21 16:53:53 +08:00
Mike Frysinger a99bbccd87 Blackfin arch: force irq_flags into the .data section
force irq_flags into the .data section by initializing it to
the hardware masks that cannot be disabled.  this way if we
use irq enable/disable functions before the .bss has been
zeroed out (as does our l1 relocate/dma functions), we dont
hit a problem where bss contains bogus crap.

Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-10-22 00:19:31 +08:00
Michael Hennerich 590031450a Blackfin arch: add new processor ADSP-BF52x arch/mach support
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-10-21 16:54:27 +08:00
Mike Frysinger f0b5d12f2b Blackfin arch: allow people to select the feature that is unavailable to the kernel
- allow people to select the feature that is unavailable to the kernel: NMI, JTAG, or CYCLES.
 - change default NMI handler to simply dump hardware trace buffer.
 - remove default NMI handler completely as calling into kernel code is not safe
   move example handler to wiki so people dont haphazardly copy and paste this stuff thinking its safe

Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-08-05 17:03:59 +08:00
Mike Frysinger a298049180 Blackfin arch: remove unused code -- EVT0 is not controllable by software
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-08-03 18:29:15 +08:00
Michael Hennerich 6782ea9ae8 Blackfin arch: Add label to call new GPIO API
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-24 15:16:59 +08:00
Michael Hennerich 50e163ce8e Blackfin arch: add error message when IRQ no available
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-24 16:17:28 +08:00
Bernd Schmidt 8be80ed3f7 Blackfin arch: Initialize the exception vectors early in the boot process
Initialize the exception vectors early in the boot process, so that CPLB faults
can be handled when memory protection is enabled.

Signed-off-by: Bernd Schmidt <bernd.schmidt@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-25 14:44:49 +08:00
Bryan Wu c04d66bbbd Blackfin arch: clean up some coding style issues
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-12 17:26:31 +08:00
Michael Hennerich e3f2300036 Blackfin arch: Some memory and code optimizations - Fix SYS_IRQS
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-12 16:39:29 +08:00
Michael Hennerich 34e0fc89bd Blackfin arch: Enable BF54x PIN/GPIO interrupts
Signed-off-bu: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-12 16:17:18 +08:00
Mike Frysinger 1f83b8f148 Blackfin arch: cleanup warnings from checkpatch -- no functional changes
Signed-off-by: Mike Frysinger <michael.frysinger@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-12 22:58:21 +08:00
Michael Hennerich 1c5d2265a8 Blackfin arch: add missing implementations SIC_IWR crosses several registers
SIC_IWR crosses several registers
 - add missing implementations
 - make sure SIC_IWR is SET after boot

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-06-21 11:34:16 +08:00
Roy Huang 24a07a1241 Blackfin arch: initial supporting for BF548-EZKIT
The ADSP-BF54x was specifically designed to meet the needs of convergent multimedia
applications where system performance and cost are essential ingredients. The
integration of multimedia, human interface, and connectivity peripherals combined
with increased system bandwidth and on-chip memory provides customers a platform to
design the most demanding applications.

Since now, ADSP-BF54x will be supported in the Linux kernel and bunch of related drivers
such as USB OTG, ATAPI, NAND flash controller, LCD framebuffer, sound, touch screen will
be submitted later.

Please enjoy the show.

Signed-off-by: Roy Huang <roy.huang@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-07-12 22:41:45 +08:00
Simon Arlott d2d50aa97d Blackfin arch: spelling fixes
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
2007-06-11 15:31:30 +08:00
Bryan Wu 1394f03221 blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix!  Tinyboards.

The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc.  (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000.  Since then ADI has put this core into its Blackfin
processor family of devices.  The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set.  It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.

The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf

The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc

This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/

We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel

[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-07 12:12:58 -07:00