When live configuring a FLL configuration with no synchroniser disable the
synchroniser in case the previous configuration used one.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
For optimal performance the FLL loop gain should be adjusted depending on
the frequency of the input clock for the loop.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
If we are using a high freqency SYNCCLK then increasing the bandwidth of
the synchroniser improves performance.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
If there is only one clock active the FLL should use REFCLK rather than
SYNCCLK as the clock to synchronise with since REFCLK is always required.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Enabling the FLL when REFCLK is being configured is not what the user
would expect and can cause issues if SYNCCLK has no specified frequency.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Since we are automatically managing the mutes we may as well also manage
the volume update bits, disabling volume updates while none of the inputs
are active. Since we are doing this we may as well allow the volumes to
ramp together so only enable volume updates once at the end of power up.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch allows the REFCLK to be set directly allowing much greater
flexibility in how the FLLs are configured.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Previously updates that only changes FLL source would be missed, this
patch corrects this. We also ensures that both REFCLK and SYNCCLK
frequency changes are considered, in preparation for future updates.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
In preparation for additional features on the FLL this patch factors out
the code for enabling an FLL into a seperate function.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
In preparation for additional features on the FLL this patch factors out
the code for disabling an FLL into a seperate function.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
In preparation for additional features on the FLL this patch factors out
the code which checks if an FLL is currently enabled into a seperate
function.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
This patch caches the current SYNCCLK settings in the arizona_fll struct
and uses these to simplify the code which determines which source should
be used for the REFCLK and SYNCCLK inputs.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
In preparation for additional features on the FLL this patch moves the
code selecting the REFCLK source based on the 32kHz clock into the FLL
initialisation function.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
For optimal performance the inputs should be kept muted until after power
up. Since there are few use cases for muting inputs during capture move
the mutes to automatic control.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Previously arizona_calc_fll() was checking if the target frequency is
exactly divisible by reference frequency, but should have been product
of the ratio and the reference frequency.
Also scale down the Lamba and Theta coefficients be under 16-bits in
order to match the registers.
Signed-off-by: Ryo Tsutsui <ryo.tsutsui@wolfsonmicro.com>
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@vger.kernel.org
Place a cap on the number of channels clocks are generated for. This is
intended for use with systems which have the WM5102 master an I2S bus with
multiple data lines.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Some systems may wish to support switching between telephony and CD audio
clock rates but this is restricted by enforcement of constraints on the
current DAI clock. Support setting clocks to zero and don't enforce any
constraints in that case in order to facilitate this use case.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Otherwise we'll get the wrong LRCLK if we need to pick a higher BCLK than
is required.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@vger.kernel.org
We only log the result and since the interrupt triggers on loss of lock
during shutdown this may lead to spurious interrupts during shutdown
delaying the process.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
The free running mode can cause problems when attempting to bring up the
FLL running from a defined clock source. This patch disables
free-running mode.
Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
In preparation for more advanced sample rate managment move the existing
code out of the main hw_params() function.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Some systems use external analogue switches to connect more analogue
devices to the CODEC than are supported by the device. In some systems
this requires changing the switched output from single ended to
differential mode dynamically at runtime. Add a new function
arizona_set_output_mode() to support this.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
ARIZONA_AIF1_RATE_MASK is 0x7800 /* AIF1_RATE - [14:11] */
Thus we need left shift ARIZONA_AIF1_RATE_SHIFT when setting aif1 rate.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@vger.kernel.org
So the code to suppress duplicate changes is effective.
Reported-by: Kyung Kwee Ryu <Kyung-Kwee.Ryu@wolfsonmicro.comyu@wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Provide robustness against low quality FLL sync clocks by increasing the
timeout for lock to an absurdly high point; we should never get anywhere
near hitting the timeout in a real system unless it is failing.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Dimitris Papastamos <dp@opensource.wolfsonmicro.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@vger.kernel.org
Arizona devices support two output system clocks. Provide support for
configuring these via set_sysclk(). Once the clock API is more useful
we should migrate over to that.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Some Arizona chips have a higher frequency for the FLL VCO, support this
in the common code.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
