The dapm field of the snd_soc_codec struct is eventually going to be
removed, in preparation for this replace all manual access to
codec->dapm.bias_level with snd_soc_codec_get_bias_level().
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
All drivers have the same line at the end of the set_bias_level callback to
update the bias_level state. Move this update into
snd_soc_dapm_force_bias_level() and remove them from the drivers.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@kernel.org>
Now that the kernel provides DIV_ROUND_CLOSEST_ULL(), drop the internal
implementation and use the kernel one.
Signed-off-by: Javi Merino <javi.merino@arm.com>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Cc: Peter Rosin <peda@axentia.se>
Acked-by: Mark Brown <broonie@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
A selection of changes for v4.1 so far. The main things are:
- Move of jack registration to the card where it belongs.
- Support for DAPM routes specified by both the machine driver and DT.
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Merge tag 'asoc-v4.1' into asoc-next
ASoC: Changes for v4.1
A selection of changes for v4.1 so far. The main things are:
- Move of jack registration to the card where it belongs.
- Support for DAPM routes specified by both the machine driver and DT.
# gpg: Signature made Thu 05 Mar 2015 01:10:27 GMT using RSA key ID 5D5487D0
# gpg: WARNING: digest algorithm MD5 is deprecated
# gpg: please see https://gnupg.org/faq/weak-digest-algos.html for more information
# gpg: Oops: keyid_from_fingerprint: no pubkey
# gpg: Good signature from "Mark Brown <broonie@sirena.org.uk>"
# gpg: aka "Mark Brown <broonie@debian.org>"
# gpg: aka "Mark Brown <broonie@kernel.org>"
# gpg: aka "Mark Brown <broonie@tardis.ed.ac.uk>"
# gpg: aka "Mark Brown <broonie@linaro.org>"
# gpg: aka "Mark Brown <Mark.Brown@linaro.org>"
Currently GPIO4 is hardcoded to output the pll-lock signal.
Unfortunately this is after the pll-out GPIO is configured which
is selectable in the device tree. Therefore it is not possible to
use GPIO4 for pll-out. Therefore this patch removes the
configuration of GPIO4.
Signed-off-by: Howard Mitchell <hm@hmbedded.co.uk>
Signed-off-by: Mark Brown <broonie@kernel.org>
If den=1 and pllin_rate>20MHz then den and num are adjusted to 0
causing a divide by zero error a few lines further on. Therefore
this patch correctly scales num and den such that
pllin_rate/den < 20MHz as required in the device data sheet.
Signed-off-by: Howard Mitchell <hm@hmbedded.co.uk>
Signed-off-by: Mark Brown <broonie@sirena.org.uk>
Cc: stable@vger.kernel.org
This is to ensure that 'alsactl restore' does not apply default
initialisation as the chip reset defaults are preferred.
Signed-off-by: Howard Mitchell <hm@hmbedded.co.uk>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
When using non-standard rates, a relatively small amount of overclocking
can make a big difference to a number of cases.
- Not all rates are possible to achieve with the PLL, due to divider
restrictions.
- The higher oversampling rates that can be used by the DAC, the
simpler the analog output filters get (mirror frequencies move up,
away from the desired spectrum).
- The more work the DSP can perform per sample, the better.
For standard rates, there is little to gain as everything is
designed just right, and the needed overclocking to make a
real difference would be significant.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
This was overlooked in the late change to remove the I2S padding bits
from S24_LE mode. The patch also limits S32_LE mode to 384kHz, the
maximum according to the datasheets.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
The PLL introduces jitter, which in turn introduces noice if used
to clock the DAC. Thus, avoid the PLL output, and use the PLL input
to drive the DAC clock, if possible.
This is described for the PCM5142/PCM5242 chips in the answers to the
forum post "PCM5142/PCM5242 DAC clock source" at the TI E2E community
pages (1).
(1) http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/389994
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
Using the PLL in master mode requires using an external connection
between one of the GPIO pins (configured as PLL/4 output) and the
SCK pin. It also requires the external clock to be fed to some other
GPIO pin instead of the SCK pin.
This is described for the PCM5122 chip in the answers to the forum post
"PCM5122 DAC as I2S master troubles with PLL mode" at the TI E2E
community pages (1). The clocking functionality is also much better
described in the datasheet for the chip PCM5242, which seems to be
register compatible with PCM512x and PCM514x (which both have severely
lacking datasheets).
(1) http://e2e.ti.com/support/data_converters/audio_converters/f/64/t/267830
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
Use register field names from the seemingly compatible PCM5242 datasheet,
as the PCM512x and PCM514x datasheets are severly lacking.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
The DSP programs are listed out of order.
Signed-off-by: Peter Rosin <peda@axentia.se>
Signed-off-by: Mark Brown <broonie@kernel.org>
Cc: stable@vger.kernel.org
After commit b2b49ccbdd (PM: Kconfig: Set PM_RUNTIME if PM_SLEEP is
selected) PM_RUNTIME is always set if PM is set, so #ifdef blocks
depending on CONFIG_PM_RUNTIME may now be changed to depend on
CONFIG_PM.
Replace CONFIG_PM_RUNTIME with CONFIG_PM everywhere under sound/.
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Takashi Iwai <tiwai@suse.de>
Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
Acked-by: Brian Austin <brian.austin@cirrus.com>
Acked-by: Mark Brown <broonie@kernel.org>
SOC_VALUE_ENUM is deprecated and merely an alias for SOC_ENUM. Replace the
deprecated macro so we can eventually remove their definition.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
Fixes the following compilation warnings:
sound/soc/codecs/pcm512x.c:520:12: warning: ‘pcm512x_suspend’ defined but not used [-Wunused-function]
sound/soc/codecs/pcm512x.c:545:12: warning: ‘pcm512x_resume’ defined but not used [-Wunused-function]
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
Move to the new style of defining the bus interfaces in separate modules
in order to simplify dependencies.
Signed-off-by: Mark Brown <broonie@linaro.org>
There are some analogue volume controls in page 1 of the register map so
implement support for them now that we can access the registers.
Signed-off-by: Mark Brown <broonie@linaro.org>
The PCM512x devices use a paged register map covering the entire register
range. Implement support for this, mapping pages in at addresses starting
at 0x100 for ease of use (though since the pages are numbered from 0 there
is going to be an off by one when looking at the first byte as a page
number).
Also mark the new registers as accessible with the exception of the
coefficient RAM which is a bit fiddly and may benefit from some extra
handling to linearise the blocks.
Signed-off-by: Mark Brown <broonie@linaro.org>
Since the core now takes const strings for enums we should be constifying
them (and the regulator supplies while we're at it).
Reported-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mark Brown <broonie@linaro.org>
The PCM512x devices are a family of monolithic CMOS integrated circuits
that include a stereo digital-to-analog converter and additional support
circuitry.
This is an initial driver which supports some core functionality for the
device which covers common use cases but does not cover all features.
Currently only slave clocking modes with automatic clock configuration
are supported and most of the DSP configuration for the device is not
enabled.
Signed-off-by: Mark Brown <broonie@linaro.org>
