Add INTC_IRQ_PINS_16H to allow broken out support of the
the high 16 external interrupt pins. On SoCs with 32 external
interrupt pins the interrupt vectors for the low 16 and the
high 16 interrupt pins are sparesly populated. The low 16 are
at 0x0200 and high 16 are at 0x3200 which with current macros
results in a separation of 384 linux interrupts. This sparse
population makes it unsuitable with a single IRQ domain to
cover the full IRQ range, so this macro breaks out the 32 pins
into two separate 16 bit controllers to allow two independent
INTC instances with two separate IRQ domains.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add a INTC_PINT() macro with various helper bits to allow SoCs
like sh73a0 to suppor the PINT hardware using regular INTC tables.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add INTC_IRQ_PINS_16() and INTC_IRQ_PINS_32() to mach/intc.h.
These macros define 16 or 32 external IRQ pins on a certain
memory base address. Can be used with INTCA or INTCS.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
