3 commits

Author	SHA1	Message	Date
Santosh Shilimkar	6cfc229d6f	clk: keystone: Build Keystone clock drivers ... Now build the keystone common clock drivers. The build is made conditional based on COMMON_CLK_KEYSTONE Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>	2013-10-07 18:16:37 -07:00
Santosh Shilimkar	7affe5685c	clk: keystone: Add gate control clock driver ... Add the driver for the clock gate control which uses PSC (Power Sleep Controller) IP on Keystone 2 based SOCs. It is responsible for enabling and disabling of the clocks for different IPs present in the SoC. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>	2013-10-07 18:16:30 -07:00
Santosh Shilimkar	b9e0d40c0d	clk: keystone: add Keystone PLL clock driver ... Add the driver for the PLL IPs found on Keystone 2 devices. The PLL IP typically has a multiplier, a divider and a post-divider. The PLL IPs like ARMPLL, DDRPLL and PAPLL are controlled by the memory mapped register where as the Main PLL is controlled by a PLL controller and memory map registers. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>	2013-10-07 18:16:21 -07:00