Now that u5500 is obsolete, u8500 is the only user of the Nomadik
i2c driver. As such there is no requirement to differentiate between
initialisation values. By the time a new SoC is released, almost all
of the ux500 platform will be DT:ed, so we can make decisions based
on the compatible property instead.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Allow proper initialisation for MMC via the mmci driver
for the Snowball low-cost development board using DT. At
the moment we continue to use DMA setup from platform code.
Once the DMA generic DT bindings have been completed we
can then port the remainder over to DT.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
On some platform it may happen that the input clock to keyboard may
change during suspend, thus impacting its wakeup capability.
There is no means for keyboard driver to know this frequency before
hand. Hence introduce a platform data 'suspended_rate' which indicates
the frequency during suspend at which keyboard operates.
Accordingly reprogram keyboard while going into suspend and restore
original configuration at the time of resume.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Checking for adc->ts_pend already claimed should be done with the
lock held.
Signed-off-by: Todd Poynor <toddpoynor@google.com>
Acked-by: Ben Dooks <ben-linux@fluff.org>
Cc: Stable <stable@vger.kernel.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The rate of xusbxti clock is set in individual machine files.
The default value should be defined at the clock definition
and individual machine files should modify it if required.
Division by zero in kernel.
[<c0011849>] (unwind_backtrace+0x1/0x9c) from [<c022c663>] (Ldiv0+0x9/0x12)
[<c022c663>] (Ldiv0+0x9/0x12) from [<c001a3c3>] (s3c_setrate_clksrc+0x33/0x78)
[<c001a3c3>] (s3c_setrate_clksrc+0x33/0x78) from [<c0019e67>] (clk_set_rate+0x2f/0x78)
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Cc: Stable <stable@vger.kernel.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add node for EXYNOS4 interrupt combiner controller.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The set_level callback in the controller data, which is used to configure
the slave select line, cannot be supported when migrating the driver to
device tree based discovery. Since all the platforms currently use gpio
as the slave select line, this callback can be removed from the
controller data and replaced with call to gpio_set_value in the driver.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
With the spi controller hardware configuration moved into the driver data, there
are no more default hardware configuration data that is passed through platform
data. Accordingly, the s3c64xx_spi{0|1|2}_set_platdata functions are adapted to
these changes.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The platform data pointer that is passed to the spi gpio setup functions
is not used. Hence, this parameter is removed from all the spi gpio setup
functions.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Platform data is used to specify controller hardware specific information
such as the tx/rx fifo level mask and bit offset of rx fifo level. Such
information is not suitable to be supplied from device tree. Instead,
it can be moved into the driver data and removed from platform data.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Jaswinder Singh <jaswinder.singh@linaro.org>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Commit 4972a80e16 (ARM: SAMSUNG: Add device tree support for pl330 dma
engine wrappers) introduced a new member 'dt_dmach_prop' in the struct
samsung_dma_info which is used to specify the dma channel number property
as obtained from the device tree. It also introduced a new dma request id
'DMACH_DT_PROP' to indicate that a device tree node property represting
the dma channel is available in 'struct samsung_dma_info'.
Add dma request id 'DMACH_DT_PROP' in s3c64xx dma channel id list in order
to maintain compatibility to the changes in the Samsung dma wrappper
operations.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Make it easier to switch to the common clock API by making the existing
clock API implementation depend on a Kconfig symbol which is enabled when
the common clock API is disabled. This means that we can have some SoCs
using the common clock API and some using the existing API rather than
needing a flag day to convert the entire family of devices over.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
arch/arm/mach-exynos/pmu.c:318:14: warning:
symbol 'exynos5_list_both_cnt_feed' was not declared. Should it be static?
arch/arm/mach-exynos/pmu.c:332:14: warning:
symbol 'exynos5_list_diable_wfi_wfe' was not declared. Should it be static?
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Fixes the following warning:
arch/arm/mach-exynos/common.c:543:13:
warning: symbol 'combiner_init' was not declared. Should it be static?
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Adds clock setting entries for EXYNOS4212 and EXYNOS4412 platforms.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
[fixed compilation warning which is reported by Arnd Bergmann]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Use cpu compatibility field and clock-frequency field of DT to
estimate the capacity of each core of the system and to update
the cpu_power field accordingly.
This patch enables to put more running tasks on big cores than
on LITTLE ones. But this patch doesn't ensure that long running
tasks will run on big cores and short ones on LITTLE cores.
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This factorization has also been proposed in another patch that has not been
merged yet:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-January/080873.html
So, this patch could be dropped depending of the state of the other one.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add infrastructure to be able to modify the cpu_power of each core
Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Reviewed-by: Namhyung Kim <namhyung@kernel.org>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
From Shawn Guo <shawn.guo@linaro.org>:
Here is the second (last) batch of mxs mxs device tree changes for 3.6.
* 'mxs/dt-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: dts: imx28-evk: add usb devices
ARM: mxs: rename dts files with soc name being the prefix
ARM: apx4devkit: add pin muxing for GPIOs
ARM: apx4devkit: remove AUART3
ARM: apx4devkit: add SSP2 support
ARM: apx4devkit: fix the bus-width of SSP0 to 4 bits
ARM: apx4devkit: add display support
ARM: apx4devkit: add NAND support
ARM: mxs: add dtb-y target into Makefile.boot
ARM: mxs: convert stmp378x_devb board to device tree
ARM: mxs: convert tx28 board to device tree
ARM: mxs: convert apx4devkit board to device tree
ARM: mxs: convert m28evk board to device tree
ARM: dts: imx28: move lcdif control pins into board dts
ARM: dts: imx28: move extra gpmi-nand pins into board dts
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'imx-defconfig' of git://git.pengutronix.de/git/imx/linux-2.6 into next/defconfig
From Sascha Hauer <s.hauer@pengutronix.de>:
ARM i.MX defconfig updates for v3.6
* tag 'imx-defconfig' of git://git.pengutronix.de/git/imx/linux-2.6:
ARM: imx_v4_v5_defconfig: update features
ARM: imx_v6_v7_defconfig: update features
Includes an update to v3.5-rc5
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Shawn Guo <shawn.guo@linaro.org>:
Here is the second (last) batch of imx device tree changes for 3.6.
* 'imx/dt-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: imx6q: ensure ANATOP controller is available
ARM: dts: imx6q-sabrelite: add ecspi1 pinctrl support
ARM: dts: imx6q-sabrelite: add usb devices
ARM: imx6q: disable usb charger detector
ARM: imx6q: add usbphy clocks
ARM: imx6q: add usb controller clock lookups
ARM: dts: imx: update #interrupt-cells for gpio nodes
bindings: update imx and mxs #gpio-cells
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Sascha Hauer <s.hauer@pengutronix.de>:
ARM i.MX dt updates for v3.6
* tag 'imx-dt' of git://git.pengutronix.de/git/imx/linux-2.6:
arm/dts: Add support for i.MX31 bug 1.x board from buglabs.
ARM i.MX31: Add devicetree support
ARM: dts: Add basic support for mx27_3ds board
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Tony Lindgren <tony@atomide.com>:
Device tree related patches for omaps
* tag 'omap-devel-dt-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
arm/dts: New dts file for PandaBoardES (4460)
arm/dts: omap4-panda: Audio support for PandaBoard 4430
arm/dts: omap4-sdp: Enable audio support via device tree
arm/dts: omap4-sdp: Add support for twl6040
arm/dts: omap4-sdp: Add fixed regulator to represent VBAT
arm/dts: omap4: Add entry for OMAP DMIC IP
arm/dts: omap4: Add entry for OMAP McPDM IP
arm/dts: am33xx wdt node
arm/dts: remove MMC/SD and SPI related entries from am33xx.dtsi
watchdog: omap_wdt: add device tree support
ARM: OMAP: avoid build wdt platform device if with dt support
arm/dts: add wdt node for omap3 and omap4
arm/dts: OMAP4: Add Variscite OMAP4 System-On-Modeule support
arm/dts: Add support for AM335x BeagleBone
arm/dts: Add support for AM335x EVM
arm/dts: Add initial DT support for AM33XX SoC family
arm/dts: omap3-evm: Add i2c and twl4030 support
arm/dts: Add support for TI AM3517/05 EVM board
arm/dts: OMAP2: Add support for OMAP2420H4 Board
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Nicolas Ferre <nicolas.ferre@atmel.com>:
Two new boards described with device tree
* tag 'at91-for-next-dt' of git://github.com/at91linux/linux-at91:
ARM: at91: Add support for board aks-cdu
ARM: at91: add support for Telit EVK-PRO3 with Telit GE863-PRO3
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch contains changes to Tegra device tree files, and related
Kconfig and Makefile changes. Highlights are:
* New support for the Whistler board.
* Use of the I2C pinctrl-based bus mux on Seaboard/Springbank.
This branch is based on Tegra's for-3.6/cleanup branch from a previous
pull request.
* 'for-3.6/dt' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: dt: tegra seaboard: move battery monitor to mux'd I2C bus.
ARM: dt: tegra: seaboard: instantiate pinctrl-based I2C bus mux
ARM: dt: tegra: add Whistler device tree file
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Imported from mailing list
* picoxcell/timer:
clocksource: dw_apb_timer: Add common DTS glue for dw_apb_timer
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Make a common device tree glue for clocksource/dw_apb_timer.
Move mach-picoxcell/time.c to be a generic device tree application
of the dw_apb_timer.
Configure mach-picoxcell to use the dw_apb_timer_of device tree
implementation in drivers/clocksource.
Signed-off-by: Pavel Machek <pavel@denx.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Jamie Iles <jamie@jamieiles.com>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
... in preparation for common clock coming for Integrator
and Versatile Express.
Based on Linus Walleij's "ARM: integrator: convert to common
clock" patch.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
With recent enough motherboard firmware, core tile can be fitted
in either of the two daughterboard sites. The non-DT tile code for
V2P-CA9 did not check that when configuring DVI output nor setting
CLCD pixel clock.
Fixed now, providing "get master site" API in motherboard's code.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
The vexpress Kconfig setup tries to be clever^Whelpful and selects some
errata workarounds for certain revisions of the Cortex-A9 and PL310,
which may be required depending on the core tile.
Since the mach-vexpress can support A5, A7 and A15 coretiles, let's
make errata workaround selection optional.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Rob Herring <robherring2@gmail.com>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
From Roland Stigge <stigge@antcom.de>:
This is the pull request including the fix for the compile error caused
by lpc32xx-next and dma branches collisions in linux-next.
* 'lpc32xx/core-fixes' of git://git.antcom.de/linux-2.6:
ARM: LPC32xx: Adjust to pl08x DMA interface changes
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This patch adjusts the LPC32xx platform support to the new pl08x DMA interface,
fixing the compile error resulting from changed pl08x structures.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Commit ca1d72f033 ('PM / Domains: Make it possible to add devices to
inactive domains') introduced possibility to add devices to inactive
power domains and added pm_genpd_dev_need_restore() function which lets
platform core to notify power domain core that the specified device must
be restored (with its runtime_resume() callback) before first use.
This patch adds the pm_genpd_dev_need_restore() call what brings back
the suspend/resume behaviour for the client devices known from the
previous power domain driver (removed by commit 91cfbd4ee0 - 'ARM:
EXYNOS: Hook up power domains to generic power domain infrastructure').
Client device drivers relay on that suspend/resume behaviour, thus this
patch fixes runtime pm operation for client devices.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Some bootloaders disable unused power domains to reduce power
consuption. Power domain driver can easily read the actual state from
the hardware registers instead of assuming that their initial state is
always 'on'.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
When SYS_WDTRESET is set, watchdog timer reset request
is ignored by power management unit.
Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
During imx6q initialization the usb charger detector is disabled but
for it, ANATOP controller symbols need to be available.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Cc: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Imx6q sabrelite board uses ecspi1 to connect a spi flash sst25vf016b,
we need to add pinctrl information for it in the dts, otherwise the
ecspi1 driver can't work and the connected flash is wrongly
detected as a mr25h256 flash like this:
m25p80 spi32766.0: found mr25h256, expected sst25vf016b
m25p80 spi32766.0: mr25h256 (32 Kbytes)
Cc: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Hui Wang <jason77.wang@gmail.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The external charger detector needs to be disabled,
or the signal at DP will be poor
Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds real clock support to Calxeda Highbank SOC using the common
clock infrastructure.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
[mturquette@linaro.org: fixed up invalid writes to const struct member]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This converts the Integrator platform to use common clock
and the ICST driver. Since from this point not all ARM
reference platforms use the clock, we define
CONFIG_PLAT_VERSATILE_CLOCK and select it for all platforms
except the Integrator.
Open issue: I could not use the .init_early() field of the
machine descriptor to initialize the clocks, but had to
move them to .init_irq(), so presumably .init_early() is
so early that common clock is not up, and .init_machine()
is too late since it's needed for the clockevent/clocksource
initialization. Any suggestions on how to solve this is
very welcome.
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[mturquette@linaro.org: use 'select' instead of versatile Kconfig]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
All the Integrator devices have bus names like "mb:16" which
I think means "memory base 0x16000000" which is where the
UART0 is. So let's call it "uart0" because that's what most
platforms do these days.
Change this everywhere for the integrator as we prepare for
some core clock code movement.
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This converts the U300 clock implementation over to use the common
struct clk and moves the implementation down into drivers/clk.
Since VCO isn't used in tree it was removed, it's not hard to
put it back in if need be.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[mturquette@linaro.org: trivial Makefile conflict]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
* renesas-board-common:
ARM: mach-shmobile: select the fixed regulator driver on several boards
regulator: extend the fixed dummy voltage regulator to accept voltage
regulator: support multiple dummy fixed regulators
Conflicts:
arch/arm/mach-shmobile/Kconfig
* renesas-soc: (31 commits)
ARM: shmobile: Fix build problem in pm-sh7372.c for unusual .config
ARM: shmobile: Take cpuidle dependencies into account correctly
ARM: mach-shmobile: sh7377 generic board support via DT
ARM: mach-shmobile: r8a7740 generic board support via DT
ARM: shmobile: sh7372: completely switch over to using pm-rmobile API
ARM: shmobile: ap4evb: switch to using pm-rmobile API
ARM: shmobile: mackerel: switch to using pm-rmobile API
ARM: shmobile: sh7372: add pm-rmobile domain support
ARM: shmobile: r8a7740: add A4LC pm domain support
ARM: shmobile: r8a7740: add A3SP pm domain support
ARM: shmobile: r8a7740: add A4S pm domain support
ARM: shmobile: r8a7740: fixup: MSEL1CR 7bit control
ARM: shmobile: soc-core: add R-mobile PM domain common APIs
ARM: shmobile: sh7372 A3SM CPUIdle support
ARM: shmobile: Use INTCA with sh7372 A3SM power domain
ARM: mach-shmobile: Convert sh_clk_mstp32_register to sh_clk_mstp_register
ARM: shmobile: use common DMAEngine definitions on sh7372
ARM: shmobile: use common DMAEngine definitions on sh73a0
ARM: shmobile: sh73a0: add DMAEngine support for MPDMAC
ARM: shmobile: sh73a0: add USB clock support
...
* renesas-sh7372:
ARM: shmobile: Fix build problem in pm-sh7372.c for unusual .config
ARM: shmobile: Take cpuidle dependencies into account correctly
ARM: shmobile: sh7372: completely switch over to using pm-rmobile API
ARM: shmobile: ap4evb: switch to using pm-rmobile API
ARM: shmobile: mackerel: switch to using pm-rmobile API
ARM: shmobile: sh7372: add pm-rmobile domain support
ARM: shmobile: sh7372 A3SM CPUIdle support
ARM: shmobile: Use INTCA with sh7372 A3SM power domain
ARM: shmobile: use common DMAEngine definitions on sh7372
ARM: shmobile: sh7372: remove unused sh7372_a3sp_init() on !CONFIG_PM
* renesas-sh73a0:
ARM: shmobile: use common DMAEngine definitions on sh73a0
ARM: shmobile: sh73a0: add DMAEngine support for MPDMAC
ARM: shmobile: sh73a0: add USB clock support
* renesas-r8a7740:
ARM: mach-shmobile: r8a7740 generic board support via DT
ARM: shmobile: r8a7740: add A4LC pm domain support
ARM: shmobile: r8a7740: add A3SP pm domain support
ARM: shmobile: r8a7740: add A4S pm domain support
ARM: shmobile: r8a7740: fixup: MSEL1CR 7bit control
ARM: shmobile: use common DMAEngine definitions on r8a7740
ARM: shmobile: r8a7740: add DMAEngine support for USB
ARM: shmobile: r8a7740: add DMAEngine support for SDHI
ARM: shmobile: r8a7740: add DMAEngine support for FSI
* renesas-fixes:
ARM: shmobile: r8a7779: Route all interrupts to ARM
ARM: shmobile: kzm9d: use late init machine hook
ARM: shmobile: kzm9g: use late init machine hook
ARM: mach-shmobile: armadillo800eva: Use late init machine hook
This is required for udev to run which is common to many user-spaces.
It is my understanding that this is a requirement for automated
testing conducted by Iwamatsu-san.
Signed-off-by: Simon Horman <horms@verge.net.au>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
If neither CONFIG_SUSPEND nor CONFIG_CPU_IDLE is set in the kernel
configuration file, build error occurs in
arch/arm/mach-shmobile/pm-sh7372.c.
Fix it by rearranging #ifdefs in that file to make the
definition of sh7372_suspend_init() depend only on
CONFIG_SUSPEND and the definition of sh7372_cpuidle_init()
depend only on CONFIG_CPU_IDLE.
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Acked-by: Magnus Damm <damm@opensource.se>
The sh7372's cpuidle code uses cpu_suspend() and cpu_resume() in
its implementation of the .enter() callback for deeper C-states, so
make ARCH_SH7372 select ARM_CPU_SUSPEND if CPU_IDLE is set to satisfy
all of the build dependencies (it has to be selected for CONFIG_PM
as well for the system suspend handling).
[rjw: Added the subject and changelog.]
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
* multiple omap2+ bug fixes
* a regression on ux500 dt support
* a build failure on shmobile
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
- multiple omap2+ bug fixes
- a regression on ux500 dt support
- a build failure on shmobile
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: OMAP2+: omap2plus_defconfig: EHCI driver is not stable, disable it
ARM: shmobile: fix platsmp.c build when ARCH_SH73A0=n
ARM: ux500: Over-ride the DT device naming scheme for pinctrl
ARM: ux500: Fix build errors/warnings when MACH_UX500_DT is not set
of: address: Don't fail a lookup just because a node has no reg property
ARM: OMAP2+: hwmod code/clockdomain data: fix 32K sync timer
Rename mxs dts files with soc name being the prefix, so that the board
dts file can be located easily by soc name, and we also gain the
consistency of naming.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
- Add sound support
- Enable mtd support
- Enable i.MX NAND support
- Enable NOR flash support
- Enable JFFS2/UBI
- Enable clk debugfs support
- Disable iommu support which is not present on i.MX
- Enable MC13xxx RTC
- Enable RNGA random number generator
- Enable SPI EEPROM support
- Enable I2C EEPROM support
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
AUART3 is not available anymore. Pins are used as GPIOs.
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add HannStar display and device tree configuration.
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add dtb-y target into Makefile.boot, so that "make ARCH=arm dtbs" can
build out all the dtbs listed there. It's very useful for build-testing
all the <board>.dts when imx28.dtsi changes.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The enc28j60 spi device does not get converted to dts file, because
there is no mxs spi driver on mainline so far. The enc28j60 spi
in mach-stmp378x_devb.c does not work anyway.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
FEC support is missing because we need to find a proper way to rewrite
tx28_add_fec0 for device tree boot.
Cc: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The presence and muxing of lcdif control pins can vary much on different
boards. Move them into imx28-evk.dts to make lcdif_24bit_pins_a only
about data pins, so that it can be reused by other boards.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Only pins GPMI_CE0N and GPMI_READY0 are generally used by other boards.
Move GPMI_CE1N and GPMI_READY1 into imx28-evk.dts to make gpmi_pins_a
more general, and can be used by other boards.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Nicolas Royer <nicolas@eukrea.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Eric Bénard <eric@eukrea.com>
Tested-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Only the main UART and the memory node information are added.
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds basic devicetree support for i.MX31 based SoCs.
Only the UART and interrupts bindings are added.
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
From Tony Lindgren <tony@atomide.com>:
This branch contains minimal support for omap5 to boot to a
console without clock framework support. This branch depends
on omap-cleanup-part2-for-v3.6.
* 'devel-omap5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: Kconfig update to support additional GPIOs in OMAP5
ARM: OMAP5: Add the build support
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: board-generic: Add device tree support
ARM: omap2+: board-generic: clean up the irq data from board file
ARM: OMAP5: Add SMP support
ARM: OMAP5: Add the WakeupGen IP updates
ARM: OMAP5: l3: Add l3 error handler support for omap5
ARM: OMAP5: gpmc: Update gpmc_init()
ARM: OMAP5: timer: Add clocksource, clockevent support
ARM: OMAP5: Add minimal support for OMAP5430 SOC
ARM: OMAP5: id: Add cpu id for ES versions
ARM: OMAP: counter-32k: Select the CR register offset using the IP scheme
ARM: OMAP2+: Move stubbed secure_sram_reserve function to a common.c and call it __weak
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
will use the common clock framework, but those patches are not quite
ready yet for omaps. This branch depends on omap-cleanup-part2-for-v3.6
branch.
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Merge tag 'omap-devel-am33xx-data-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/clk
From Tony Lindgren <tony@atomide.com>:
This branch adds clock data for am33xx. Note that eventually these
will use the common clock framework, but those patches are not quite
ready yet for omaps. This branch depends on omap-cleanup-part2-for-v3.6
branch.
* tag 'omap-devel-am33xx-data-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP3+: clock33xx: Add AM33XX clock tree data
ARM: OMAP3+: clock: Move common clksel_rate & clock data to common file
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fix an interrupt handling issue with cp_intc which
was causing occasional spurious interrupts with DA850 EVM
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Merge tag 'davinci-v3.6-fixes' of git://gitorious.org/linux-davinci/linux-davinci into next/fixes-non-critical
DaVinci fixes for v3.6
Fix an interrupt handling issue with cp_intc which
was causing occasional spurious interrupts with DA850 EVM
* tag 'davinci-v3.6-fixes' of git://gitorious.org/linux-davinci/linux-davinci:
ARM: davinci: da8xx: fix interrupt handling
Add IRQ domain support for cp_intc and
runtime PM core support for DaVinci devices.
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Merge tag 'davinci-v3.6-soc' of git://gitorious.org/linux-davinci/linux-davinci into next/soc
From Sekhar Nori <nsekhar@ti.com>:
DaVinci SoC updates for v3.6
Add IRQ domain support for cp_intc and
runtime PM core support for DaVinci devices.
* tag 'davinci-v3.6-soc' of git://gitorious.org/linux-davinci/linux-davinci:
ARM: davinci: add runtime PM support for clock management
ARM: davinci: cp_intc: Add irq domain support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Remove some header files which were marked for removal. These files are
not used anymore.
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Merge tag 'davinci-v3.6-cleanup' of git://gitorious.org/linux-davinci/linux-davinci into next/cleanup
From: Sekhar Nori <nsekhar@ti.com>
DaVinci cleanups for v3.6
Remove some header files which were marked for removal. These files are
not used anymore.
* tag 'davinci-v3.6-cleanup' of git://gitorious.org/linux-davinci/linux-davinci:
ARM: davinci: remove dummy header files
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
echi-omap because the driver currently causes issues with PM.
This annoys Kevin as it makes it harder for him to validate that
PM is working. The proper fixes for the echi-omap are being
discussed, but looks like it will not be properly working with PM
until in v3.7.
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Merge tag 'omap-fixes-for-v3.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
From Tony Lindgren <tony@atomide.com>:
Here is one PM regression fix and a defconfig change to disable
echi-omap because the driver currently causes issues with PM.
This annoys Kevin as it makes it harder for him to validate that
PM is working. The proper fixes for the echi-omap are being
discussed, but looks like it will not be properly working with PM
until in v3.7.
* tag 'omap-fixes-for-v3.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: omap2plus_defconfig: EHCI driver is not stable, disable it
ARM: OMAP2+: hwmod code/clockdomain data: fix 32K sync timer
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Read the number of MPIC interrupts from the controller and only register
that many.
[gregory.clement@free-electrons.com: rename armada symbol name to fit
with new name: armada_370_xp]
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
[ben.dooks@codethink.co.uk: ensure error check on of_property_read_u32]
[ben.dooks@codethink.co.uk: use mpic address instead of bus-unit's ]
[ben.dooks@codethink.co.uk: BUG_ON() if the of_iomap() fails for mpic]
[ben.dooks@codethink.co.uk: move mpic per-cpu register base ]
[ben.dooks@codethink.co.uk: number fetch should use irqd_to_hwirq()]
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Lior Amsalem <alior@marvell.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Yehuda Yitschak <yehuday@marvell.com>
Tested-by: Lior Amsalem <alior@marvell.com>
From Kukjin Kim <kgene.kim@samsung.com>:
* 'next/board-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C64XX: Add IRQ mapping for wm0010 on Cragganmore
ARM: S5PV210: Add HSOTG support to SMDKV210
ARM: EXYNOS: Update keypad entries for SMDK4X12
ARM: S3C64XX: Dynamically assign interrupts for CPU PMIC on Cragganmore
ARM: S3C64XX: Dynamically allocate the IRQ range for WM8994 on Cragganmore
ARM: S3C64XX: Add WM5102 EVM to Cragganmore modules
ARM: S3C64XX: Add module identification for Balblair Cragganmore module
ARM: EXYNOS: Add HSOTG support to SMDKV310
ARM: EXYNOS: Add HSOTG support to Origen
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Kukjin Kim <kgene.kim@samsung.com>:
Here is updating DMA common operation for Samsung SoCs.
Since some DMA client driver such as spi needs to change the configuration
after dma_request() so this branch adds dma_config() can configure DMA
transmit option which is included in dma_request() after that.
Note, according to the changes, needs to update spi and ASoC drivers
for Samsung SoCs and only got the ack from Mark Brown not Grant Likely
and as I know, he is busy for moving. But I think, the spi change has
no problem and it is simple.
* 'next/devel-dma-ops' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: SAMSUNG: Fix compiler warning in dma-ops.c file
ASoC: follow the updated samsung DMA common operations
spi/s3c64xx: Add the use of DMA config operation
ARM: SAMSUNG: Add config() function in DMA common operations
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Kukjin Kim <kgene.kim@samsung.com>:
Samsung cleanup patches for v3.6 and most of them are removing
useless codes
* 'next/cleanup-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Remove the L2 cache latency setting for EXYNOS5
ARM: EXYNOS: Remove leftovers of the Samsung specific power domain control
ARM: SAMSUNG: Remove unused variable 'running' on PWM
ARM: SAMSUNG: remove unused SPI clock headers
ARM: S3C24XX: remove unused header <mach/bast-pmu.h>
ARM: S3C24XX: Remove duplicate header file inclusion
ARM: SAMSUNG: Remove description corresponding to a deleted element
ARM: S5PC100: Remove unused variable in dma.c file
ARM: S5P64X0: Remove unused variable in dma.c file
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
sparse found this assignment of u32 to an int. Fix it:
drivers/i2c/busses/i2c-imx.c:540:56: warning: incorrect type in argument 3 (different signedness)
and also fix the type in platform_data. All current users use values
which fit into the old and new type, so it is a safe change.
Signed-off-by: Wolfram Sang <wolfram@the-dreams.de>
Reviewed-by: Richard Zhao <richard.zhao@freescale.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Commit cb8ca5897 (ARM: omap3evm: enable VBUS switch for EHCI tranceiver)
added a new randconfig error if TWL4030_CORE is not selected:
arch/arm/mach-omap2/board-omap3evm.c:368: undefined reference to `twl_i2c_read_u8'
arch/arm/mach-omap2/board-omap3evm.c:370: undefined reference to `twl_i2c_write_u8'
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add support for our "aks-cdu" board based up on Telit's module GE863 Pro3.
It has more uarts, leds, another nand partitioning.
Signed-off-by: Jiri Prchal <jiri.prchal@aksignal.cz>
[nicolas.ferre@atmel.com: correction of the dts file]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The syscall_trace on ARM takes a `why' parameter to indicate whether or
not we are entering or exiting a system call. This can be confusing for
people looking at the code since (a) it conflicts with the why register
alias in the entry assembly code and (b) it is not immediately clear
what it represents.
This patch splits up the syscall_trace function into separate wrappers
for syscall entry and exit, allowing the low-level syscall handling
code to branch to the appropriate function.
Reported-by: Al Viro <viro@zeniv.linux.org.uk>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When auditing system calls on ARM, the audit code is called before
notifying the parent process in the case that the current task is being
ptraced. At this point, the parent (debugger) may choose to change the
system call being issued via the SET_SYSCALL ptrace request, causing
the wrong system call to be reported to the audit tools.
This patch moves the audit calls after the ptrace SIGTRAP handling code
in the syscall tracing implementation.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ret_from_fork is setup for a freshly spawned child task via copy_thread,
called from copy_process. The latter function clears TIF_SYSCALL_TRACE
and also resets the child task's audit_context to NULL, meaning that
there is little point invoking the system call tracing routines.
Furthermore, getting hold of the syscall number is a complete pain and
it looks like the current code doesn't even bother.
This patch removes the syscall tracing checks from ret_from_fork.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch allows a timer-based delay implementation to be selected by
switching the delay routines over to use get_cycles, which is
implemented in terms of read_current_timer. This further allows us to
skip the loop calibration and have a consistent delay function in the
face of core frequency scaling.
To avoid the pain of dealing with memory-mapped counters, this
implementation uses the co-processor interface to the architected timers
when they are available. The previous loop-based implementation is
kept around for CPUs without the architected timers and we retain both
the maximum delay (2ms) and the corresponding conversion factors for
determining the number of loops required for a given interval. Since the
indirection of the timer routines will only work when called from C,
the sa1100 sleep routines are modified to branch to the loop-based delay
functions directly.
Tested-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch implements read_current_timer using the architected timers
when they are selected via CONFIG_ARM_ARCH_TIMER. If they are detected
not to be usable at runtime, we return -ENXIO to the caller.
Furthermore, if read_current_timer is exported then we can implement
get_cycles in terms of it for use as both an entropy source and for
implementing __udelay and friends.
Tested-by: Shinya Kuribayashi <shinya.kuribayashi.px@renesas.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
DCACHE_WORD_ACCESS uses the word-at-a-time API for optimised string
comparisons in the vfs layer.
This patch implements support for load_unaligned_zeropad for ARM CPUs
with native support for unaligned memory accesses (v6+) when running
little-endian.
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch implements the word-at-a-time interface for ARM using the
same algorithm as x86. We use the fls macro from ARMv5 onwards, where
we have a clz instruction available which saves us a mov instruction
when targetting Thumb-2. For older CPUs, we use the magic 0x0ff0001
constant. Big-endian configurations make use of the implementation from
asm-generic.
With this implemented, we can replace our byte-at-a-time strnlen_user
and strncpy_from_user functions with the optimised generic versions.
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
In order to provide PMU name strings compatible with the OProfile
user ABI, an enumeration of all PMUs is currently used by perf to
identify each PMU uniquely. Unfortunately, this does not scale well
in the presence of multiple PMUs and creates a single, global namespace
across all PMUs in the system.
This patch removes the enumeration and instead uses the name string
for the PMU to map onto the OProfile variant. perf_pmu_name is
implemented for CPU PMUs, which is all that OProfile cares about anyway.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The ARM arch_{read,write}_trylock implementations include unused
backwards branch labels, since we don't retry the locking operation
if the exclusive store fails.
This patch removes the labels.
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Ticket spinlocks ensure locking fairness by introducing a FIFO-like
nature to the granting of lock acquisitions and also reducing the
thundering herd effect when spinning on a lock by allowing the cacheline
to remain in a shared state amongst the waiting CPUs. This is especially
important on systems where memory-access times are not necessarily
uniform when accessing the lock structure (for example, on a
multi-cluster platform where the lock is allocated into L1 when a CPU
releases it).
This patch implements the ticket spinlock algorithm for ARM, replacing
the simpler implementation for ARMv6+ processors.
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch introduces a new Kconfig option which, when enabled, causes
the kernel to write the PID of the current task into the PROCID field
of the CONTEXTIDR on context switch. This is useful when analysing
hardware trace, since writes to this register can be configured to emit
an event into the trace stream.
The thread notifier for writing the PID is deliberately kept separate
from the ASID-writing code so that we can support newer processors using
LPAE, where the ASID is stored in TTBR0. As such, the switch_mm code is
updated to perform a read-modify-write sequence to ensure that we don't
clobber the PID on CPUs using the classic 2-level page tables.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When a CPU is shutdown its architected timer comparators registers are
lost. Within CPU idle, before processors enter shutdown they enter
clock events broadcast mode through the
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, cpuid);
function where the local timers are emulated by a global always-on timer.
On CPU resume, the per-CPU tick device normal mode is restored by exiting
broadcast mode through
clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, cpuid);
In order for this mechanism to function, architected timers should add to
their feature C3STOP, which means that they are not able to function when the
CPU is in off-mode.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Commit 64ac24e738 ("Generic semaphore
implementation") removed the last include of this header. Apparently it
was just an oversight to keep this header. It can safely be removed now.
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Let's map the initial RAM up to the end of the kernel .bss instead of
the strict kernel image area. This simplifies the code as the kernel
image only needs to be handled specially in the XIP case. That covers
the legacy ATAG location as well.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This patch allows the ATAG_CMDLINE provided by the bootloader to be
concatenated to the bootargs property of the device tree.
This is useful to merge static values defined in the device tree
with the boot loader's (possibly) more dynamic values, such as
startup reasons and more.
The bootloader should use the device tree to pass those values to
the kernel, but that's not always simple (old bootloader or very
small one).
The behaviour is the same as the one introduced by Victor Boivie in
4394c12442 by extending the CONFIG_CMDLINE.
Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The vectors page has been traditionally mapped as WT on UP systems but
this creates a mismatched alias with the directly mapped RAM that is
using WB attributes. On newer processors like Cortex-A15 this has
implications on the data/instructions coherency at the point of
unification (usually L2).
This patch removes such restriction.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Robustify ARM's die() handling with improvements from x86:
- Fix for a deadlock (before panic in the case of panic_on_oops) if we
oops under a spinlock which is also used from interrupt handler,
since the old code was unconditionally enabling interrupts.
- Usage of arch spinlock so lockdep etc doesn't get involved while
we're trying to dump out oopses.
- Deadlock prevention in the unlikely event that die() recurses.
The changes all touch the same few lines of code, so they're done
together in one patch.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Make the OS timer registers have IOMEM like properities so they can
be passed to readl_relaxed/writel_relaxed() et.al. rather than being
straight volatile dereferences. Add linux/io.h includes where
required.
linux/io.h includes added to arch/arm/mach-sa1100/cpu-sa1100.c,
arch/arm/mach-sa1100/jornada720_ssp.c, arch/arm/mach-sa1100/leds-lart.c
drivers/input/touchscreen/jornada720_ts.c, drivers/pcmcia/sa1100_shannon.c
from Arnd.
This fixes these warnings:
arch/arm/mach-sa1100/time.c: In function 'sa1100_timer_init':
arch/arm/mach-sa1100/time.c:104: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type
arch/arm/mach-pxa/time.c: In function 'pxa_timer_init':
arch/arm/mach-pxa/time.c:126: warning: passing argument 1 of 'clocksource_mmio_init' discards qualifiers from pointer target type
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
While running hotplug tests I ran into this RCU splat
===============================
[ INFO: suspicious RCU usage. ]
3.4.0 #3275 Tainted: G W
-------------------------------
include/linux/rcupdate.h:729 rcu_read_lock() used illegally while idle!
other info that might help us debug this:
RCU used illegally from idle CPU!
rcu_scheduler_active = 1, debug_locks = 0
RCU used illegally from extended quiescent state!
4 locks held by swapper/2/0:
#0: ((cpu_died).wait.lock){......}, at: [<c00ab128>] complete+0x1c/0x5c
#1: (&p->pi_lock){-.-.-.}, at: [<c00b275c>] try_to_wake_up+0x2c/0x388
#2: (&rq->lock){-.-.-.}, at: [<c00b2860>] try_to_wake_up+0x130/0x388
#3: (rcu_read_lock){.+.+..}, at: [<c00abe5c>] cpuacct_charge+0x28/0x1f4
stack backtrace:
[<c001521c>] (unwind_backtrace+0x0/0x12c) from [<c00abec8>] (cpuacct_charge+0x94/0x1f4)
[<c00abec8>] (cpuacct_charge+0x94/0x1f4) from [<c00b395c>] (update_curr+0x24c/0x2c8)
[<c00b395c>] (update_curr+0x24c/0x2c8) from [<c00b59c4>] (enqueue_task_fair+0x50/0x194)
[<c00b59c4>] (enqueue_task_fair+0x50/0x194) from [<c00afea4>] (enqueue_task+0x30/0x34)
[<c00afea4>] (enqueue_task+0x30/0x34) from [<c00b0908>] (ttwu_activate+0x14/0x38)
[<c00b0908>] (ttwu_activate+0x14/0x38) from [<c00b28a8>] (try_to_wake_up+0x178/0x388)
[<c00b28a8>] (try_to_wake_up+0x178/0x388) from [<c00a82a0>] (__wake_up_common+0x34/0x78)
[<c00a82a0>] (__wake_up_common+0x34/0x78) from [<c00ab154>] (complete+0x48/0x5c)
[<c00ab154>] (complete+0x48/0x5c) from [<c07db7cc>] (cpu_die+0x2c/0x58)
[<c07db7cc>] (cpu_die+0x2c/0x58) from [<c000f954>] (cpu_idle+0x64/0xfc)
[<c000f954>] (cpu_idle+0x64/0xfc) from [<80208160>] (0x80208160)
When a cpu is marked offline during its idle thread it calls
cpu_die() during an RCU idle period. cpu_die() calls complete()
to notify the killing process that the cpu has died. complete()
calls into the scheduler code and eventually grabs an RCU read
lock in cpuacct_charge().
Mark complete() as RCU_NONIDLE so that RCU pays attention to this
CPU for the duration of the complete() function even though it's
in idle.
Suggested-by: "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
OMAP5 has 8 GPIO banks so that there are 32x8 = 256 GPIOs.
In order for the gpiolib to detect and initialize these
additional GPIOs and other TWL GPIOs, ARCH_NR_GPIO is set
to 512 instead of present 256.
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Cc: Cousson, Benoit <b-cousson@ti.com>
Reported-by: Govindraj.R <govindraj.raja@ti.com>
Tested-by: Govindraj.R <govindraj.raja@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Adding the build support required for OMAP5 soc
in to omap2+ config.
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Adding the minimum device tree files required for
OMAP5 to boot.
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Adding the minimal support for OMAP5 evm board
with device tree.
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Move the irq_match arrays and the irq init functions of OMAP 2,3
and 4 based boards out of board-generic.c file and also rename the
irq init function to match the interrupt controller present in
the SOCs.
This is a preparatory patch to add the OMAP5 evm board's irq init
support with device tree.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Add OMAP5 SMP boot support using OMAP4 SMP code. The relevant code paths
are runtime checked using cpu id
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP4 and OMAP5 share same WakeupGen IP with below few udpates on OMAP5.
- Additional 32 interrupt support is added w.r.t OMAP4 design.
- The AUX CORE boot registers are now made accessible from non-secure SW.
- SAR offset are changed and PTMSYNC* registers are removed from SAR.
Patch updates the WakeupGen code accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
The l3 interconnect ip is same for OMAP4 and OMAP5.
So reuse the l3 error handler error code for OMAP5
as well. Also a few targets has been newly added for
OMAP5. So updating the driver for that here.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
GPMC module is the same as in OMAP4.
Just update the base address and irq number.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Adding the Initialisaton for clocksource and clockevent device
on OMAP5 Socs.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP5430 is Texas Instrument's SOC based on ARM Cortex-A15 SMP
architecture. It's a dual core SOC with GIC used for interrupt
handling and with an integrated L2 cache controller.
OMAP5432 is another variant of OMAP5430, with a
memory controller supporting DDR3 and SATA.
Patch includes:
- The machine specific headers and sources updates.
- Platform header updates.
- Minimum initialisation support for serial.
- IO table init
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Adding the OMAP5 ES1.0, 2.0 and OMAP5432 cpu revision
detection support.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
OMAP socs has a legacy and a highlander version of the
32k sync counter IP. The register offsets vary between the
highlander and the legacy scheme. So use the 'SCHEME'
bits(30-31) of the revision register to distinguish between
the two versions and choose the CR register offset accordingly.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
omap_secure_ram_reserve_memblock is stubbed for OMAP1,2 only builds using a
ifdef check. But this results in adding CONFIG_ARCH_OMAPxx checks for
future socs that use the real function. So move this to common.c file and
call it __weak.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
The 4430 and 4460 version of PandaBoard mostly the same with
exception at least in audio setup.
Use the omap4-panda.dts file as a base and only override the differences
between the revisions.
For audio it is the name of the sound card and the routing information.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
PandaBoard uses twl6040 connected via McPDM for audio.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On OMAP4 SDP the audio setup includes the twl6040 codec and digital
microphones.
Since OMAP4 SDP is a reference board it has all possible audio interfaces
connected. This information is passed via the ti,audio-routing
property.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The twl6040 provides the audio and vibra support on OMAP4 SDP boards.
It is connected to i2c1 bus with 0x4b address.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DMIC IP is used to connect up to 6 digital microphones directly to OMAP.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
McPDM is used on OMAP4 based boards to communicate with an external audio
codec (twl6040).
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The sys_nirq2 is used for twl6040, make sure the pin is configured
correctly.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The sys_nirq2 is used for twl6040, make sure the pin is configured
correctly.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
CP_INTC code in entry-macro.S code reads SECR1n register to see if
an interrupt was indeed pending. This register is actually marked as
write-only in the OMAP-L138 TRM. Moreover, the code just checks to see
the entire register is non-zero and does not check a specific interrupt
number.
Fix this to use interrupt pending bit in GIPR register for this purpose.
GIPR register is already being read to know the highest priority interrupt
pending.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The i2c-nomadik gateware is really a PrimeCell APB device. By hosting
the driver under the amba bus we can access it more easily, for
example using the generic pci-amba driver. The patch also fixes the
mach-ux500 users, so they register an amba device instead than a
platform device.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
The header and driver are only used by arm/mach-u8500 (and potentially
arm/mach-nomadik), but the STA2X11 I/O Hub exports on PCIe a number of
devices, including i2c-nomadik. This patch allows compilation of the
driver under x86.
Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
The MMC/SD and SPI entries in this file are not tested yet. They
inadvertently came into the patch because of some work in progress
stuff I had in my repo.
These entries should not have been sent out in the first place and
I am sorry for the trouble and will be extra careful in future.
Since the offending commit is not sent upstream yet, I hope this can
be merged into the commit 5fc0b42a98
(arm/dts: Add initial DT support for AM33XX SoC family) on the devel-dt
branch of linux-omap tree.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
If provided dt support, then skip add wdt platform device as usual.
Signed-off-by: Xiao Jiang <jgq516@gmail.com>
Reviewed-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
OMAP4 only build breaks with below error
arch/arm/mach-omap2/sdrc.c:135: error: redefinition of 'omap2_sdrc_init'
arch/arm/plat-omap/include/plat/sdrc.h:130: note: previous definition of 'omap2_sdrc_init' was here
make[1]: *** [arch/arm/mach-omap2/sdrc.o] Error 1
Fix the same by using newly introduced CONFIG_SOC_HAS_OMAP2_SDRC marco.
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch completes commit 08406f5 by fixing the following issues, according to
the reference manual:
* MXC_OTG_UCTRL_OPM_BIT disables (masks) the power/oc pins if set, like H1PM and
H2PM, not the opposite.
* MXC_OTG_PHYCTRL_OC_DIS_BIT disables the oc pin if set, like H1_OC_DIS, not the
opposite.
* Typos in comments.
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org>
Cc: <linux-arm-kernel@lists.infradead.org>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Make ehci power and overcurrent polarities configurable. If not set, these new
configurartions keep the default register values so that existing board files
do not have to be changed.
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: <linux-arm-kernel@lists.infradead.org>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Now that RTC support has been enabled for i.MX35, add RTC to the mx35_3ds board.
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: <linux-arm-kernel@lists.infradead.org>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The i.MX35 has an RTC compatible with the i.MX31's, so enable its support even
if it's not very useful because it's not battery backed.
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: <linux-arm-kernel@lists.infradead.org>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The data sheet of the i.MX35 says it is an ARM1136JF-S processor, version r1p3,
which, according to section "B.1. New instructions" of the ARM1136JF-S and
ARM1136J-S Technical Reference Manual, makes the i.MX35 CPU architecture not
only ARMv6, but ARMv6k.
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: <linux-arm-kernel@lists.infradead.org>
Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This patch adds missing definitions for DISP, GPT and CCM pads.
These pins are not used by kernel, but may be helpful for custom boards.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Add a very basic dt support for mx27_3ds (also known as mx27pdk).
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
The EHCI driver is not stable enough to be enabled by default. In v3.5,
it has at least the following problems:
- warning dump during bootup
- hang during suspend
- prevents CORE powerdomain from entering retention during idle (even
when no USB devices connected.)
This demonstrates that this driver has not been thoroughly tested and
therfore should not be enabled in the default defconfig.
In addition, the problems above cause new PM regressions which need be
addressed before this driver should be enabled in the default
defconfig.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Prior to the new i.mx clock conversion the mx27 silicon version was printed at boot.
Reenable this feature.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
As the AB8500 is a subordinate MFD device to the DB8500-PRCMU,
for consistency and a better 1:1 depiction of how the hardware
is laid out, it is a good idea to register it in the same way
as we do for the other MFD child devices. In order for us to do
this successfully we have to pass AB8500's platform data when
registering the DB8500-PRCMU from platform code.
Also solves this issue:
WARNING: at fs/sysfs/dir.c:526 sysfs_add_one+0x88/0xb0()
sysfs: cannot create duplicate filename '/bus/platform/devices/ab8500-core.0'
Reported-by: Linus Walleij <linus.walleij@linaro.org>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Add irq domain support for max8997 interrupts. The reverse mapping method
used is linear mapping since the sub-drivers of max8997 such as regulator
and charger drivers can use the max8997 irq_domain to get the linux irq
number for max8997 interrupts. All uses of irq_base in platform data and
max8997 driver private data are removed.
Reviwed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Acked-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Now the MFD API is Device Tree aware we can use it for platform
registration again, even when booting with DT enabled. To aid in
Device Node pointer allocation we provide each cell with the
associative compatible string.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Hierarchically, the AB8500 is a child of the DB8500 PRCMU. So now that
Device Tree is being used and MFD core code is Device Tree aware, we
can simply register DB8500 PRCMU from Device Tree in the normal way
then allow the DB8500 PRCMU driver to register the AB8500 as a simple
MFD device at probe time.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
This allows use a Debian armhf usespace
as well as the existing ability to use a Debian armel userspace.
Signed-off-by: Simon Horman <horms@verge.net.au>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Pull ARM fixes from Russell King:
"Last merge window, we had some updates from Al cleaning up the signal
restart handling. These have caused some problems on ARM, and while
Al has some fixes, we have some concerns with Al's patches but we've
been unsuccesful with discussing this.
We have got to the point where we need to do something, and we've
decided that the best solution is to revert the appropriate commits
until Al is able to reply to us.
Also included here are four patches to fix warnings that I've noticed
in my build system, and one fix for kprobes test code."
* 'fixes' of git://git.linaro.org/people/rmk/linux-arm:
ARM: fix warning caused by wrongly typed arm_dma_limit
ARM: fix warnings about atomic64_read
ARM: 7440/1: kprobes: only test 'sub pc, pc, #1b-2b+8-2' on ARMv6
ARM: 7441/1: perf: return -EOPNOTSUPP if requested mode exclusion is unavailable
ARM: 7443/1: Revert "new way of handling ERESTART_RESTARTBLOCK"
ARM: 7442/1: Revert "remove unused restart trampoline"
ARM: fix set_domain() macro
ARM: fix mach-versatile/pci.c warning
Change the value of #interrupt-cells of gpio nodes from 1 to 2, so that
the gpio irq type can be specified in device tree. Also update binding
document to make it clear.
Reported-by: Sascha Hauer <s.hauer@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
From Stephen Warren <swarren@wwwdotorg.org>:
This branch contains a single commit which adjusts tegra_defconfig to
enable new kernel features, driven by new device tree file content and drivers.
* 'for-3.6/defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: defconfig updates
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Stephen Warren <swarren@wwwdotorg.org>:
This branch contains numerous changes required as a baseline in order to
convert Tegra to the common clock framework. The intention was to also
include patches to actually convert Tegra to the common clock framework.
However, those patches appeared late in the kernel cycle and currently
cause regressions on some boards, so were dropped for now.
* 'for-3.6/common-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: Provide clock for only one PWM controller
ARM: tegra: Fix PWM clock programming
ARM: tegra: dma: rename driver name for clock to "tegra-apbdma"
ARM: tegra: Remove second instance of uart clk
crypto: add clk_prepare/clk_unprepare
ASoC: tegra: add clk_prepare/clk_unprepare
staging: nvec: add clk_prepare/clk_unprepare
spi/tegra: add clk_prepare/clk_unprepare
Input: tegra-kbc - add clk_prepare/clk_unprepare
USB: ehci-tegra: add clk_prepare/clk_unprepare
mmc: tegra: add clk_prepare/clk_unprepare
i2c: tegra: Add clk_prepare/clk_unprepare
ARM: tegra: add clk_prepare/clk_unprepare
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Stephen Warren <swarren@wwwdotorg.org>
This branch contains changes to Tegra board files, and related Kconfig and
Makefile changes. Highlights include:
* Removal of Seaboard/Springbank board files; these boards can now only be
used with device tree.
* Use of small parts of some non-DT board files from the DT board files. This
enables all features that the non-DT board files have, when booting from DT.
This will allow almost complete removal of all non-DT board files in v3.7.
* Other miscellaneous changes.
This branch is based on Tegra's for-3.6/cleanup branch from a previous pull
request.
* 'for-3.6/boards' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: use of_default_bus_match_table
ARM: tegra: add device tree AUXDATA for APBDMA
ARM: tegra: paz00: enable WiFi rfkill when booting from device tree
ARM: tegra: harmony: init regulators, PCIe when booting from DT
ARM: tegra: trimslice: enable PCIe when booting from device tree
ARM: tegra: remove Seaboard board files
ARM: tegra: remove CONFIG_MACH_TEGRA_DT
ARM: tegra: make .dts compilation depend on Tegra2 support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Stephen Warren <swarren@wwwdotorg.org>:
This branch contains changes to Tegra SoC-specific code in the
mach-tegra directory; only APBIO/DMA-related patches this time around.
* 'for-3.6/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra: apbio: use dmaengine based dma driver
ARM: tegra: apbio access using dma for tegra20 only
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Fix build error in the case of SMP=y but ARCH_SH73A0=n
introduced by:
9601e87 ARM: shmobile: fix smp build
The use of of_machine_is_compatible() will link in the
the SoC-specific symbols:
"sh73a0_get_core_count", "sh73a0_smp_prepare_cpus",
"sh73a0_secondary_init" and "sh73a0_boot_secondary".
This patch adds an ugly #ifdef wrapper as a stop-gap
solution.
Signed-off-by: Magnus Damm <damm@opensource.se>
Tested-by: Tested-by: Simon Horman <horms@verge.net.au>
Acked-by: "Rafael J. Wysocki" <rjw@sisk.pl>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Lee Jones <lee.jones@linaro.org>:
* ux500/fixes-3.5:
ARM: ux500: Over-ride the DT device naming scheme for pinctrl
ARM: ux500: Fix build errors/warnings when MACH_UX500_DT is not set
of: address: Don't fail a lookup just because a node has no reg property
I ended up rebasing Lee's branch on 3.5-rc5 because we have more patches
lined for 3.6 that depend on them, and I want to keep all branches in
arm-soc be based on -rc releases rather than random commits in the
upstream history.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
When pin control mapping tables are written the registered device
name is supplied for use in name-based searches within the pinctrl
driver. In the case of the DB8500 the string "pinctrl-db8500" is
used. However, when we register the driver with Device Tree, its
naming convention uses something that looks more like "pinctrl.2".
To work around the device naming inconsistencies between devices
registered via platform code and the ones registered by Device
Tree, we use AUXDATA to over-ride the Device Tree naming scheme.
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
When MACH_UX500_DT and all related Device Tree configurations are forced
off the warning and error below prevent the kernel from compiling. This
simple patch fixes both issues and allows for full build and boot of
ST-Ericsson's low-cost development board, Snowball.
Warnings fixed:
arch/arm/mach-ux500/board-mop500.c:680:32: warning: ‘snowball_of_platform_devs’ defined but not used
Errors fixed:
arch/arm/mach-ux500/timer.c: In function ‘ux500_timer_init’:
arch/arm/mach-ux500/timer.c:66:3: error: implicit declaration of function ‘of_find_matching_node’
arch/arm/mach-ux500/timer.c:66:6: warning: assignment makes pointer from integer without a cast
Cc: stable@vger.kernel.org
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Two bug fixes for the previous state of the imx sparse irq changes.
* 'imx/sparse-irq' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: imx: select USE_OF
ARM: imx: Fix build error due to missing irqs.h include
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
From Shawn Guo <shawn.guo@linaro.org>:
* 'mxs/defconfig-for-3.6' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs: defconfig: Enable CONFIG_COMMON_CLK_DEBUG
ARM: mxs_defconfig: Enable RTC driver
ARM: mxs_defconfig: Let AUART driver be built by default
ARM: mxs: Enable MACH_APX4DEVKIT
ARM: mxs: Let GPMI driver be built by default
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Add generic DT board support for the sh7377 SoC.
SCIF serial ports and timers are kept as regular
platform devices. Other on-chip and on-board devices
should be configured via the device tree.
At this point there is no interrupt controller support
in place but such code will be added over time when
proper IRQ domain support has been added to INTC.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Add generic DT board support for the r8a7740 SoC.
SCIF serial ports and timers are kept as regular
platform devices. Other on-chip and on-board devices
should be configured via the device tree.
At this point there is no interrupt controller support
in place but such code will be added over time when
proper IRQ domain support has been added to INTC.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Now, all sh7372 platforms are switched over to use pm-rmobile base PM domain,
and no one is using original sh7372_pm_domain APIs.
We can remove these, switching has been fully completed.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This patch switches ap4evb platform to use pm-rmobile base common API.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This patch switches mackerel platform to use pm-rmobile base common API.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This patch adds pm-rmobile common API base PM domain.
sh7372 CPU/platform will switch to using it from
original implementation
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Because USB Func is controlled by external IRQ mode,
it is possible to control USB under A3SP domain to reduce power.
This patch enables it.
Armadillo800eva board switchs USB Host/Func by SW1.6,
So, the device to adds into domain is selected on this patch.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
It is possible to control LCDC under A4LC domain to reduce power.
This patch enable it.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
We can control renesas_usbhs driver as 2 way which are
autonomy mode and external IRQ trigger mode.
Autonomy mode is very easy settings for platform,
but it required USB power domain always ON,
since its connection/disconnection IRQ come from it.
If platform uses external IRQ trigger mode,
USB power domain can be OFF, since its
connection/disconnection IRQ come from external IRQ.
This patch enable external IRQ mode.
Now it is possible to add USB support on A4SP domain.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This patch adds basic A4LC pm domain support.
Now, below devices can be controled by PM
MERAM, LCDC, VOU, ICBS, SDENC-Link
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
MSEL1CR 7bit selects IRQ7 source pin which was
VBUS pin or A21/MSIOF0_RSYNC/MSIOF1_TSYNC pin.
But current pfc-r8a7740 MSEL1CR 7bit setting was wrong.
This patch fix it up
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
This patch adds Renesas R-mobile series common PM domain APIs.
R-mobile CPU can use/switch this API
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Tegra's I2C2 controller can be routed to either the PTA or DDC pin group
on Seaboard. Define the pinctrl state nodes required to allow runtime
control of this routing. Instantiate a pinctrl-i2cmux I2C bus mux that
uses these pinctrl states.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Whistler is a highly configurable Tegra evaluation and development board.
This change adds support for the following specific configuration:
E1120 motherboard
E1108 CPU board
E1116 PMU board
The motherboard configuration switches are set as follows:
SW1=0 SW2=0 SW3=5
S1/S2/S3/S4 all on, except S3 7/8 are off.
Other combinations of daugher boards may work to varying degrees, but will
likely require some SW adjustment.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Original work by Magnus Damm, tested and tweaked by Simon Horman
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
On systems, using regulators to supply power to devices, if the REGULATOR
Kconfig option is disabled, regulator API stubs will be used, which often
suffices to bring a default configuration up. If REGULATOR is enabled but
respective regulator drivers are inactive, the real regulator API calls
will be used, which in the absence of drivers will fail to provide
services. This patch prevents such a problem on sh-mobile boards by
forcing REGULATOR_FIXED_VOLTAGE on if REGULATOR is selected.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Use the dmaengine based Tegra APB DMA driver for
apbio access in place of legacy Tegra APB DMA.
The new driver is selected if legacy driver is not
selected and new DMA driver is enabled through config
file.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
[swarren: s/pr_err/pr_debug/ in tegra_apb_dma_init; this condition is
expected to fire repeatedly before the DMA driver is available]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Tegra20 HW issue with accessing APBIO registers (such
as fuse registers) directly from the CPU concurrently with
APB DMA accesses has been fixed in Tegra30 and later chips.
Access these registers directly from the CPU on Tegra30
and later, and apply the workaround only for Tegra20.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Chaitanya Bandi <bandik@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Currently most ads7846 config definitions for OMAP3 series boards have
been moved to common-board-devices.c, and it is transparent for init.
And it's no very proper to do gpio_request based on get_pendown_state
since omap_ads7846_init knows everything about ads7846_config.
So it's more fit to request gpio according to the right gpio_pendown
and set debounce time conditionally. If we don't set proper debouce
time, there are flooded interrupt counters of ads7846 responding to
one time touch on screen, then the driver couldn't work very well.
This patch has been validated on 3530evm.
Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This was chosen by following the trace on the schematic from component U131
and U134 to the CPEN pin on the USB3320 device.
TWL4030.GPIO2-...->(T2_GPIO2_3V3)U131-..>nUSB2_EN-..>U134-..>EXP_nUSB2_1V8
which starts EHCI tranceiver USB3320.
This will set TWL4030.GPIO2 as output pin to drive EHCI tranceiver.
Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
EHCI PHY requires these regulators:
EVM Rev >=E --> VAUX2
EVM Rev < E --> VUSB1V5, VUSB1V8
Adding USB internal LDOs (vusb1v5 & vusb1v8) and VAUX2 to omap3evm
board file. Also removing vaux2_{1/2/3} supplies as they are not
used on omap3 evm.
But we need not to add vaux2 in twl4030_platform_data since it will
be added conditionally.
Signed-off-by: Ajay Kumar Gupta <ajay.gupta@ti.com>
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
With omap_hwmod_get_main_clk() now available, this can be passed to
clk_get() to extract the fclk and thus avoid construction of fclk name.
Corrected the timer fck name mis-match between clock44xx_data.c and
omap_hwmod_44xx_data.c. For other platforms this is already taken care.
Cc: Cousson, Benoit <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit ac5b0ea3d (Merge tag 'omap-devel-f-for-3.6'...) had a merge
conflict that somehow got incorrecly resolved in a lossy way for
commit bed9d1bb (ARM: OMAP2+: hwmod: add omap_hwmod_get_main_clk() API).
Fix the issue by applying the missing pieces.
Reported-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Commit
544496a (ARM: imx: move irq_domain_add_legacy call into avic driver)
introduced unconditional calls to irq_find_mapping and
irq_domain_add_legacy, but it's still possible to have a .config without
CONFIG_IRQ_DOMAIN=y resulting in
CC arch/arm/plat-mxc/avic.o
arch/arm/plat-mxc/avic.c: In function 'avic_handle_irq':
arch/arm/plat-mxc/avic.c:172: error: implicit declaration of function 'irq_find_mapping'
arch/arm/plat-mxc/avic.c: In function 'mxc_init_irq':
arch/arm/plat-mxc/avic.c:207: error: implicit declaration of function 'irq_domain_add_legacy'
arch/arm/plat-mxc/avic.c:208: error: 'irq_domain_simple_ops' undeclared (first use in this function)
arch/arm/plat-mxc/avic.c:208: error: (Each undeclared identifier is reported only once
arch/arm/plat-mxc/avic.c:208: error: for each function it appears in.)
arch/arm/plat-mxc/avic.c:208: warning: assignment makes pointer from integer without a cast
make[3]: *** [arch/arm/plat-mxc/avic.o] Error 1
make[2]: *** [arch/arm/plat-mxc/avic.o] Error 2
make[1]: *** [sub-make] Error 2
make: *** [all] Error 2
While selecting CONFIG_IRQ_DOMAIN would be enough, USE_OF is the future
and implies CONFIG_IRQ_DOMAIN. So select USE_OF for ARCH_MXC and drop
other explicit selects that are superflous now.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
With the common clock framework in place, it is useful to enable
CONFIG_COMMON_CLK_DEBUG option, in order to easily inspect the clock tree.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Kevin discovered that commit c8d82ff68f
("ARM: OMAP2/3: hwmod data: Add 32k-sync timer data to hwmod
database") broke CORE idle on OMAP3. This prevents device low power
states.
The root cause is that the 32K sync timer IP block does not support
smart-idle mode[1], and so the hwmod code keeps the IP block in
no-idle mode while it is active. This in turn prevents the WKUP
clockdomain from transitioning to idle. There is a hardcoded sleep
dependency that prevents the CORE_L3 and CORE_CM clockdomains from
transitioning to idle when the WKUP clockdomain is active[2], so the
chip cannot enter any device low power states.
It turns out that there is no need to take the 32k sync timer out of
idle. The IP block itself probably does not have any native idle
handling at all, due to its simplicity. Furthermore, the PRCM will
never request target idle for this IP block while the kernel is
running, due to the sleep dependency that prevents the WKUP
clockdomain from idling while the CORE_L3 clockdomain is active. So
we can safely leave the 32k sync timer in target-force-idle mode, even
while we continue to access it.
This workaround is implemented by defining a new clockdomain flag,
CLKDM_ACTIVE_WITH_MPU, that indicates that the clockdomain is
guaranteed to be active whenever the MPU is inactive. If an IP
block's main functional clock exists inside this clockdomain, and the
IP block does not support smart-idle modes, then the hwmod code will
place the IP block into target force-idle mode even when enabled. The
WKUP clockdomains on OMAP3/4 are marked with this flag. (On OMAP2xxx,
no OCP header existed on the 32k sync timer.) Other clockdomains also
should be marked with this flag, but those changes are deferred until
a later merge window, to create a minimal fix.
Another theoretically clean fix for this problem would be to implement
PM runtime-based control for 32k sync timer accesses. These PM
runtime calls would need to located in a custom clocksource, since the
32k sync timer is currently used as an MMIO clocksource. But in
practice, there would be little benefit to doing so; and there would
be some cost, due to the addition of unnecessary lines of code and the
additional CPU overhead of the PM runtime and hwmod code - unnecessary
in this case.
Another possible fix would have been to modify the pm34xx.c code to
force the IP block idle before entering WFI. But this would not have
been an acceptable approach: we are trying to remove this type of
centralized IP block idle control from the PM code.
This patch is a collaboration between Kevin Hilman <khilman@ti.com>
and Paul Walmsley <paul@pwsan.com>.
Thanks to Vaibhav Hiremath <hvaibhav@ti.com> for providing comments on
an earlier version of this patch. Thanks to Tero Kristo
<t-kristo@ti.com> for identifying a bug in an earlier version of this
patch. Thanks to Benoît Cousson <b-cousson@ti.com> for identifying
some bugs in several versions of this patch and for implementation
comments.
References:
1. Table 16-96 "REG_32KSYNCNT_SYSCONFIG" of the OMAP34xx TRM Rev. ZU
(SWPU223U), available from:
http://www.ti.com/pdfs/wtbu/OMAP34x_ES3.1.x_PUBLIC_TRM_vzU.zip
2. Table 4-72 "Sleep Dependencies" of the OMAP34xx TRM Rev. ZU
(SWPU223U)
3. ibid.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoît Cousson <b-cousson@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
Add CPUIdle support for the A3SM power domain on sh7372.
With this in place we can turn off more of the SoC during
run time and save power. Makes use of the recently introduced
sh7372 INTCA A3SM power domain wakeup support.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Convert the sh7372 A3SM power domain code to allow
waking up through INTCA and SYSC instead of only
relying on SYSC for wakeups. This allows us to
enter A3SM more or less regardless of the state
of the rest of the system.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
Small fixes on multiple ARM platforms
* A build regression from a previous fix on dove and mv78xx0
* Two fixes for recently (3.5-rc1) changed mmp/pxa code
* multiple omap2+ bug fixes
* two trivial fixes for i.MX
* one v3.5 regression for mxs
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Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Arnd Bergmann:
"Small fixes on multiple ARM platforms
- A build regression from a previous fix on dove and mv78xx0
- Two fixes for recently (3.5-rc1) changed mmp/pxa code
- multiple omap2+ bug fixes
- two trivial fixes for i.MX
- one v3.5 regression for mxs"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: apx4devkit: fix FEC enabling PHY clock
ARM: OMAP2+: hwmod data: Fix wrong McBSP clock alias on OMAP4
ARM: OMAP4: hwmod data: temporarily comment out data for the usb_host_fs and aess IP blocks
ARM: Orion: Fix WDT compile for Dove and MV78xx0
ARM: mmp: remove mach/gpio-pxa.h
ARM: imx: assert SCC gate stays enabled
ARM: OMAP4: TWL6030: ensure sys_nirq1 is mux'd and wakeup enabled
ARM: OMAP2: Overo: init I2C before MMC to fix MMC suspend/resume failure
ARM: imx27_visstrim_m10: Do not include <asm/system.h>
ARM: pxa: hx4700: Fix basic suspend/resume
The function __omap2_set_globals() can be common across all
platforms/architectures, even in case of omap4, internally it
calls same set of functions as in __omap2_set_globals() function
(except for sdrc).
This patch adds new config flag SOC_HAS_OMAP2_SDRC to handle sdrc,
so that we can reuse same function across omap2/3/4...
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
As per recent discussion on the linux-omap list, we are
moving in the direction where, we will have only architecture,
ARCH_OMAP2PLUS and all devices/platforms will be treated
as a SoC underneath.
So the first step in this direction is to adopt this change
for all new devices getting in, converting
cpu_is_am33xx/335x() ==> soc_is_am33xx/335x()
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Initially, we decided to make am33xx family of device to fall
under omap3 class (cpu_is_omap34xx() = true), since it carries
Cortex-A8 core. But while adding complete baseport support
(like, clock, power and hwmod) support, it is observed that,
we are creating more and more problems by treating am33xx device
as omap3 family, as nothing matches between them
(except cortex-A8 mpu).
So, after long discussion we have came to the conclusion that,
we should not consider am33xx device as omap3 family, instead
create separate class (SOC_AM33XX) under OMAP2PLUS.
This means, for am33xx device, cpu_is_omap34xx() will return false,
and only cpu_is_am33xx() will be true.
Please refer to the link below, for mailing-list discussion on this -
http://www.spinics.net/lists/linux-omap/msg69439.html
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
[tony@atomide.com: fixed typo, updated for soc_is changes]
Signed-off-by: Tony Lindgren <tony@atomide.com>
In order to remove unnecessary idefs, move noncore and core
dpll ops to dpll3xxx.c file (where it should have been already).
The clkops (clkops_omap3_core_dpll_ops & clkops_omap3_noncore_dpll_ops)
is used in clock data files, and dependency is already handled by
Makefile rule.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
All OMAP2PLUS based devices, builds omap-device.o target;
so just add one entry so that there is no need to patch this file
for any future OMAP2+ devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mm/init.c: In function 'arm_memblock_init':
arch/arm/mm/init.c:380: warning: comparison of distinct pointer types lacks a cast
by fixing the typecast in its definition when DMA_ZONE is disabled.
This was missed in 4986e5c7c (ARM: mm: fix type of the arm_dma_limit
global variable).
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fix:
net/netfilter/xt_connbytes.c: In function 'connbytes_mt':
net/netfilter/xt_connbytes.c:43: warning: passing argument 1 of 'atomic64_read' discards qualifiers from pointer target type
...
by adding the missing const.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
'sub pc, pc, #1b-2b+8-2' results in address<1:0> == '10'.
sub pc, pc, #const (== ADR pc, #const) performs an interworking branch
(BXWritePC()) on ARMv7+ and a simple branch (BranchWritePC()) on earlier
versions.
In ARM state, BXWritePC() is UNPREDICTABLE when address<1:0> == '10'.
In ARM state on ARMv6+, BranchWritePC() ignores address<1:0>. Before
ARMv6, BranchWritePC() is UNPREDICTABLE if address<1:0> != '00'
So the instruction is UNPREDICTABLE both before and after v6.
Acked-by: Jon Medhurst <tixy@yxit.co.uk>
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
working again.
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Merge tag 'omap-fixes-for-v3.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
PM related fixes for omaps mostly to get suspend/resume
working again.
* tag 'omap-fixes-for-v3.5-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: hwmod data: Fix wrong McBSP clock alias on OMAP4
ARM: OMAP4: hwmod data: temporarily comment out data for the usb_host_fs and aess IP blocks
ARM: OMAP4: TWL6030: ensure sys_nirq1 is mux'd and wakeup enabled
ARM: OMAP2: Overo: init I2C before MMC to fix MMC suspend/resume failure
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Replace the regular kzalloc and ioremap with the devm_ equivalent
to simplify error handling. We don't need kree() any more in
omap_dm_timer_remove().
Also added *dev* pointer to reference pdev->dev which makes the
usage shorter in code.
Cc: Cousson, Benoit <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
for 3.6. Mostly small infrastructure improvements, and preparation
for OMAP5 and AM33xx code.
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Merge tag 'omap-devel-f-for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into cleanup-part2
Miscellaneous OMAP clock, hwmod, clockdomain, and powerdomain patches
for 3.6. Mostly small infrastructure improvements, and preparation
for OMAP5 and AM33xx code.
Conflicts:
arch/arm/mach-omap2/omap_hwmod.c
arch/arm/plat-omap/include/plat/omap_hwmod.h
We currently return -EPERM if the user requests mode exclusion that is
not supported by the CPU. This looks pretty confusing from userspace
and is inconsistent with other architectures (ppc, x86).
This patch returns -EOPNOTSUPP instead.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This reverts commit 6b5c8045ec.
Conflicts:
arch/arm/kernel/ptrace.c
The new syscall restarting code can lead to problems if we take an
interrupt in userspace just before restarting the svc instruction. If
a signal is delivered when returning from the interrupt, the
TIF_SYSCALL_RESTARTSYS will remain set and cause any syscalls executed
from the signal handler to be treated as a restart of the previously
interrupted system call. This includes the final sigreturn call, meaning
that we may fail to exit from the signal context. Furthermore, if a
system call made from the signal handler requires a restart via the
restart_block, it is possible to clear the thread flag and fail to
restart the originally interrupted system call.
The right solution to this problem is to perform the restarting in the
kernel, avoiding the possibility of handling a further signal before the
restart is complete. Since we're almost at -rc6, let's revert the new
method for now and aim for in-kernel restarting at a later date.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This reverts commit fa18484d09.
We need the restart trampoline back so that we can revert a related
problematic patch 6b5c8045ec ("arm: new
way of handling ERESTART_RESTARTBLOCK").
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Avoid polluting drivers with a set_domain() macro, which interferes with
structure member names:
drivers/net/wireless/ath/ath9k/dfs_pattern_detector.c:294:33: error: macro "set_domain" passed 2 arguments, but takes just 1
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add a function to initialize the Common Platform Interrupt Controller
(cp_intc) from TI used on OMAP-L1x SoCs using a device tree node.
Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: davinci-linux-open-source@linux.davincidsp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: devicetree-discuss@lists.ozlabs.org
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Sergei Shtylyov <sshtylyov@mvista.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
management and McBSP.
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Merge tag 'omap-fixes-b-for-3.5rc' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into fixes
A few more OMAP fixes for 3.5-rc. These fix some bugs with power
management and McBSP.
Ethernet stopped to work after mxs clk framework change.
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
mx23-olinuxino is a low cost board designed by Olimex.
It has the following features:
- Freescale iMX233 ARM926J processor at 454MHz
-64 MB RAM
-SD-card connector
-TV PAL/NTSC video output
-2 USB High Speed Hosts
-Ethernet 100 Mbit
-Stereo Audio Input
-Stereo Headphones Audio Output
More information at:
http://www.olimex.com/dev/imx233-olinuxino-maxi.html
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
arch/arm/mach-versatile/pci.c: In function 'versatile_map_irq':
arch/arm/mach-versatile/pci.c:342: warning: unused variable 'devslot'
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The pinctrl code needs GPIOLIB to be enabled, so make
sure that it cannot be built otherwise. This fixes
the prima2_defconfig.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Barry Song <21cnbao@gmail.com>
The commit 503d0ea24d
ARM: OMAP4: hwmod data: Add aliases for McBSP fclk clocks
added a wrong "prcm_clk" alias for PRCM clock whereas the McBSP
driver and previous OMAPs are using "prcm_fck".
It thus lead to the following warning.
[ 47.409729] omap-mcbsp: clks: could not clk_get() prcm_fck
Fix that by changing the opt_clk role to prcm_fck.
Reported-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Tested-by: Sebastien Guiriec <s-guiriec@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The OMAP4 usb_host_fs (OHCI) and AESS IP blocks require some special
programming for them to enter idle. Without this programming, they
will prevent the rest of the chip from entering full chip idle.
To implement the idle programming cleanly, this will take some
coordination between maintainers. This is likely to take some time,
so it is probably best to leave this for 3.6 or 3.7. So, in the
meantime, prevent these IP blocks from being registered.
Later, once the appropriate support is available, this patch can be
reverted.
This second version comments out the IP block data since Benoît didn't
like removing it.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Benoît Cousson <b-cousson@ti.com>
MULTI_IRQ_HANDLER and SPARSE_IRQ are now required everywhere because
mach/irqs.h and mach/entry-macros.S are gone but the symbols are
only selected for AT91SAM9, not for the NOMMU parts.
A few files now need to include linux/io.h directly, which used to
be included through other headers that have changed.
The new at91_aic_irq_priorities variable is only used with CONFIG_OF
enabled and should not be visible otherwise.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The DMADISABLE bit is a semi-automatic bit present in sysconfig register
of some modules. When the DMA must perform read/write accesses, the
DMADISABLE bit is cleared by the hardware. But when the DMA must stop for power
management, software must set the DMADISABLE bit back to 1.
In cases where the ROMCODE/BOOTLOADER uses dma, the hardware clears the
DMADISABLE bit (but the romcode/bootloader might not set it back to 1).
In order for the kernel to start in a clean state, it is
necessary for the kernel to set DMADISABLE bit back to 1 (irrespective
of whether it's been set to 1 in romcode or bootloader).
During _reset of the (hwmod)device, the DMADISABLE bit is set so that it
does not prevent idling of the system. (NOTE: having DMADISABLE to 0,
prevents the system to idle)
DMADISABLE bit is present in usbotgss module of omap5.
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
[paul@pwsan.com: updated to apply; fixed checkpatch warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Some prm and cm registers read/write and status functions
are built only for some custom OMAP2+ builds and are stubbed
in header files for other builds under ifdef statements.
But this results in adding new CONFIG_ARCH_OMAPXXX
checks when SOCs are added in the future. So move them
to a common place for OMAP2+ and make them 'weak' implementations.
This way no new ifdefs would be required in the future and also
cleans up the existing code.
Signed-off-by: R Sricharan <r.sricharan@ti.com>
[paul@pwsan.com: unsplit quoted strings; moved PRM functions to
mach-omap2/prm_common.c; resolved sparse warnings]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Add an API to get main clock name associated with a given @oh.
This will avoid the need to construct fclk names during early
initialization in order to get fclk handle using clk_get().
Signed-off-by: Tarun Kanti DebBarma <tarun.kanti@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Cc: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
If the dpll is already locked, code can be optimized
to return much earlier than doing redundent set of lock mode
and wait on idlest.
Cc: Tony Lindgren <tony@atomide.com>
Cc: Jon Hunter <jon-hunter@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Mike Turquette <mturquette@ti.com>
Signed-off-by: Vikram Pandita <vikram.pandita@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The register is used to configure the behaviour of the CSI-2 and CCP-2
receivers. This register is available only in OMAP3630.
The original patch was submitted by Vimarsh Zutshi.
Signed-off-by: Sakari Ailus <sakari.ailus@iki.fi>
Cc: Vimarsh Zutshi <vimarsh.zutshi@gmail.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
The wake-up power domain is an alway-on power domain and so this power domain
does not have a power state status (PM_PWSTST_xxx) register that indicates the
current state. However, during the registering of the wake-up power domain the
state of the domain is queried by calling pwrdm_read_pwrst(). This actually
tries to read a register that does not exist and returns a value of 0 that
indicates that the current state is OFF. The OFF state count of the wake-up
power domain is then set to 1 and the current state to OFF. Both of which are
incorrect.
To fix this, if a power domain only supports the ON state, do not attempt to
read the power state status register and simply return ON as the current power
state.
This is based upon Tony's current linux-omap master branch.
Testing:
- Boot tested on OMAP4460 panda.
- Boot tested on OMAP3430 beagle and validated CORE RET still working (using
Paul's 32k timer patch [1]).
[1] http://marc.info/?l=linux-omap&m=134000053229888&w=2
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Acked-by: Kevin Hilman <khilman@ti.com>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
[paul@pwsan.com: edited commit message slightly]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
For OMAP3+ devices, the clock domains (CLKDMs) support one or more of the
following transition modes ...
NO_SLEEP (0x0) - A clock domain sleep transition is never initiated,
irrespective of the hardware conditions.
SW_SLEEP (0x1) - A software-forced sleep transition. The transition is initiated
when the associated hardware conditions are satisfied
SW_WKUP (0x2) - A software-forced clock domain wake-up transition is initiated,
irrespective of the hardware conditions.
HW_AUTO (0x3) - Hardware-controlled automatic sleep and wake-up transition is
initiated by the PRCM module when the associated hardware
conditions are satisfied.
For OMAP4 devices, SW_SLEEP is equivalent to HW_AUTO and NO_SLEEP is equivalent
to SW_WKUP. The only difference between HW_AUTO and SW_SLEEP for OMAP4 devices
is that the PRM_IRQSTATUS_MPU.TRANSITION_ST interrupt status is set in case of
SW_SLEEP transition, and not set in case of HW_AUTO transition.
For OMAP4 devices, all CLKDMs support HW_AUTO and therefore we can place the
CLKDMs in the HW_AUTO state instead of the SW_SLEEP mode. Hence, we do not
need to use the SW_SLEEP mode. With regard to NO_SLEEP and SW_WKUP it is
preferred to use SW_WKUP mode if the CLKDM supports it and so use this mode
instead of NO_SLEEP where possible.
For a software perspective the above 4 modes are represented by the following
flags to indicate what modes are supported by each of the CLKDMs.
CLKDM_CAN_DISABLE_AUTO --> NO_SLEEP
CLKDM_CAN_ENABLE_AUTO --> HW_AUTO
CLKDM_CAN_FORCE_SLEEP --> SW_SLEEP
CLKDM_CAN_FORCE_WAKEUP --> SW_WKUP
By eliminating the SW_SLEEP mode the the mapping of the flags for OMAP4 devices
can becomes ...
CLKDM_CAN_DISABLE_AUTO --> NO_SLEEP
CLKDM_CAN_ENABLE_AUTO --> HW_AUTO
CLKDM_CAN_FORCE_SLEEP --> HW_AUTO
CLKDM_CAN_FORCE_WAKEUP --> SW_WKUP
Cc: Ming Lei <ming.lei@canonical.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@ti.com>
Reviewed-by: Benoit Cousson <b-cousson@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Jon Hunter <jon-hunter@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
In case of AM33XX device, XXX_RSTST register offset is not
consistent across PRM modules/instances,
PRM_XXX RSTST
=========================
PRM_PER_MOD: 0x04
PRM_WKUP_MOD: 0x0C
PRM_MPU_MOD: NA
PRM_DEVICE_MOD: 0x08
This means, we need to pass on XXX_RSTST register offset
information through omap_hwmod data, similar to XXX_RSTCTRL.
Currently, this field is only applicable and used for AM33XX
devices.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Cc: Benoit Cousson <b-cousson@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Kevin Hilman <khilman@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
In case of AM33xx family of devices (like cpsw) have different sysc
bit field offsets defined,
sysc_type3:
| 3 2 | 1 0 |
| STDBYMODE | IDLEMODE |
So introduce new sysc_type3 in omap_hwmod common data.
Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Vaibhav Bedia <vaibhav.bedia@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Commit 0fa1f0609a (ARM: Orion: Fix
Virtual/Physical mixup with watchdog) broke the Dove & MV78xx0
build. Although these two SoC don't use the watchdog, the shared
platform code still needs to build. Add the necessary defines.
Cc: stable@vger.kernel.org
Reported-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Nicolas Pitre <nico@fluxnic.net>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Commit 157d2644cb ("ARM: pxa: change gpio
to platform device") removed all includes of mach/gpio-pxa.h. It kept
this unused header in the tree. Using it can't work, as it itself
includes the non-existent header plat/gpio-pxa.h. This header can safely
be removed.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Acked-by: Eric Miao <eric.y.miao@gmail.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
The SCC clock is needed in internal boot mode and so must keep enabled.
This same issue was fixed for the pre-common-clk code in commit
3d6e614 (mx35: Fix boot ROM hang in internal boot mode)
Cc: John Ogness <jogness@linutronix.de>
Cc: Hans J. Koch <hjk@hansjkoch.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
hwmod, clock, and System Control Module cleanup, and the removal
of the last instance of omap_read/write usage for omap2+ with
the removal of unused USB OHCI Full Speed driver support. The
removed OHCI is only currently used for omap1 as the actively
used omap2+ boards have either MUSB or another instance of
OHCI+EHCI that's more usable.
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mergetag object c59b537d87
type commit
tag omap-devel-dmtimer-for-v3.6
tagger Tony Lindgren <tony@atomide.com> 1341130362 -0700
Here are some omap dmtimer changes to make it easier to add
device tree support for dmtimer by simplifying the platform
data structure used by dmtimr.
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mergetag object 6fd8246b1c
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tag omap-devel-am33xx-for-v3.6
tagger Tony Lindgren <tony@atomide.com> 1341131157 -0700
Here are changes to add support for am33xx processors for the
clock, power, and voltagedomains.
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Merge tags 'omap-cleanup-for-v3.6', 'omap-devel-dmtimer-for-v3.6' and 'omap-devel-am33xx-for-v3.6' into devel-am33xx-part2
commit bc8966 (ARM: fiq: change FIQ_START to a variable) introduced the
following build error for imx_v4_v5_defconfig:
arch/arm/plat-mxc/avic.c:220:11: error: 'FIQ_START' undeclared (first use in this function)
Include the missing header file to fix it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
clock, power, and voltagedomains.
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Merge tag 'omap-devel-am33xx-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren <tony@atomide.com>:
Here are changes to add support for am33xx processors for the
clock, power, and voltagedomains.
* tag 'omap-devel-am33xx-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP AM33xx: clockdomains: Add clockdomain data and respective operations
ARM: OMAP AM33xx: powerdomains: add AM335x support
ARM: OMAP AM33xx: CM: Introduce AM33xx CM APIs and register level details
ARM: OMAP AM33xx: PRM: add PRM support
ARM: OMAP AM33xx: voltagedomain: Add voltage domain data
ARM: OMAP2+: control: Add AM33XX control reg & sec clkctrl offset
ARM: OMAP2+: am33xx: Add AM335XEVM machine support
ARM: OMAP2+: am33xx: Add low level debugging support
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
code for wake-ups, and improve idle latencies for cpuidle.
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Merge tag 'omap-devel-pm-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/pm
From: Tony Lindgren <tony@atomide.com>:
Here are some omap PM changes that reimplement omap PRCM I/O chain
code for wake-ups, and improve idle latencies for cpuidle.
* tag 'omap-devel-pm-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: PM: fix IRQ_NOAUTOEN removal by mis-merge
ARM: OMAP3: PM: cpuidle: optimize the clkdm idle latency in C1 state
ARM: OMAP3: PM: cpuidle: optimize the PER latency in C1 state
ARM: OMAP3: PM: cpuidle: default to C1 in next_valid_state
ARM: OMAP3: PM: cleanup cam_pwrdm leftovers
ARM: OMAP3: PM: call pre/post transition per powerdomain
ARM: OMAP2+: powerdomain: allow pre/post transtion to be per pwrdm
ARM: OMAP3: PM: Remove IO Daisychain control from cpuidle
ARM: OMAP3PLUS: hwmod: reconfigure IO Daisychain during hwmod mux
ARM: OMAP3+: PRM: Enable IO wake up
ARM: OMAP4: PRM: Add IO Daisychain support
ARM: OMAP3: PM: Move IO Daisychain function to omap3 prm file
ARM: OMAP3: PM: correct enable/disable of daisy io chain
ARM: OMAP2+: PRM: fix compile for OMAP4-only build
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
via the omap tree. These changes convert omap HDQ1W driver to use
runtime PM, and finally move omap SmartReflex driver from arch/arm
to live under drivers.
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Merge tag 'omap-devel-driver-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/pm
From Tony Lindgren <tony@atomide.com>:
Here are omap driver changes for v3.6 that were agreed to be merged
via the omap tree. These changes convert omap HDQ1W driver to use
runtime PM, and finally move omap SmartReflex driver from arch/arm
to live under drivers.
* tag 'omap-devel-driver-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: do not allow SmartReflex to be built as a module
ARM: OMAP2: Use hwmod to initialize mmc for 2420
W1: OMAP HDQ1W: use runtime PM
ARM: OMAP2+: HDQ1W: use omap_device
W1: OMAP HDQ1W: use 32-bit register accesses
W1: OMAP HDQ1W: allow driver to be built on all OMAP2+
ARM: OMAP: SmartReflex: Move smartreflex driver to drivers/
ARM: OMAP2+: SmartReflex: add POWER_AVS Kconfig options
ARM: OMAP2+: SmartReflex: Create per-opp debugfs node for errminlimit
ARM: OMAP2+: SmartReflex: Use per-OPP data structure
ARM: OMAP2+: Voltage: Move the omap_volt_data structure to plat
ARM: OMAP2+: SmartReflex: introduce a busy loop condition test macro
ARM: OMAP3: hwmod: rename the smartreflex entries
ARM: OMAP2+: smartreflex: Use the names from hwmod data instead of voltage domains.
ARM: OMAP3+: SmartReflex: class drivers should use struct omap_sr *
ARM: OMAP2+: SmartReflex: move the smartreflex header to include/linux/power
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
device tree support for dmtimer by simplifying the platform
data structure used by dmtimr.
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Merge tag 'omap-devel-dmtimer-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/timer
From Tony Lindgren <tony@atomide.com>:
Here are some omap dmtimer changes to make it easier to add
device tree support for dmtimer by simplifying the platform
data structure used by dmtimr.
* tag 'omap-devel-dmtimer-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Simplify dmtimer clock aliases
ARM: OMAP2+: Move dmtimer clock set function to dmtimer driver
ARM: OMAP1: Fix dmtimer support
ARM: OMAP: Add flag to indicate if a timer needs a manual reset
ARM: OMAP: Remove timer function pointer for context loss counter
ARM: OMAP: Remove loses_context variable from timer platform data
ARM: OMAP2+: Fix external clock support for dmtimers
ARM: OMAP2+: HWMOD: Correct timer device attributes
ARM: OMAP: Add DMTIMER capability variable to represent timer features
ARM: OMAP2+: Add dmtimer platform function to reserve systimers
ARM: OMAP2+: Remove unused max number of timers definition
ARM: OMAP: Remove unnecessary clk structure
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
hwmod, clock, and System Control Module cleanup, and the removal
of the last instance of omap_read/write usage for omap2+ with
the removal of unused USB OHCI Full Speed driver support. The
removed OHCI is only currently used for omap1 as the actively
used omap2+ boards have either MUSB or another instance of
OHCI+EHCI that's more usable.
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Merge tag 'omap-cleanup-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/cleanup
From Tony Lindgren <tony@atomide.com>
Here is some more omap clean-up. The biggest changes are
hwmod, clock, and System Control Module cleanup, and the removal
of the last instance of omap_read/write usage for omap2+ with
the removal of unused USB OHCI Full Speed driver support. The
removed OHCI is only currently used for omap1 as the actively
used omap2+ boards have either MUSB or another instance of
OHCI+EHCI that's more usable.
* tag 'omap-cleanup-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: hwmod: remove prm_clkdm, cm_clkdm; allow hwmods to have no clockdomain
ARM: OMAP3: Move McBSP fck clock alias to hwmod data
ARM: OMAP2: Move McBSP fck clock alias to hwmod data for OMAP2430
ARM: OMAP2: Move McBSP fck clock alias to hwmod data for OMAP2420
ARM: OMAP: dsp: interface to control module functions
ARM: OMAP2+: control: new APIs to configure boot address and mode
ARM: OMAP2+: CLEANUP: Remove ARCH_OMAPx ifdef from struct dpll_data
ARM: OMAP2+: hwmod: use init-time function pointer for _init_clkdm
ARM: OMAP2+: hwmod: use init-time function pointer for hardreset
ARM: OMAP2+: hwmod: use init-time function pointer for wait_target_ready
ARM: OMAP4: hwmod: drop extra cpu_is check from _wait_target_disable()
ARM: OMAP2+: hwmod: use init-time function ptrs for enable/disable module
ARM: OMAP4: hwmod: rename _enable_module to _omap4_enable_module()
ARM: OMAP: Make FS USB omap1 only
ARM: OMAP2: Remove legacy USB FS support
ARM: OMAP3: There is no FS USB controller on omap3
ARM: OMAP: dma: Clear status registers on enable/disable irq
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
critical enough for the 3.5 -rc cycle. The biggest changes are
fixes for the am35xx clock and hwmod data, and the removal of dead
code for the 730 and 850 headers.
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Merge tag 'omap-fixes-non-critical-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/fixes-non-critical
From Tony Lindgren <tony@atomide.com>:
This branch contains fixes that were too intrusive or not
critical enough for the 3.5 -rc cycle. The biggest changes are
fixes for the am35xx clock and hwmod data, and the removal of dead
code for the 730 and 850 headers.
* tag 'omap-fixes-non-critical-for-v3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits)
ARM: OMAP2+: fix CONFIG_CPU_IDLE dependency on CONFIG_PM
ARM: OMAP: remove unused cpu detection macros
ARM: OMAP: fix typos related to OMAP330
ARM: OMAP7XX: Remove omap730.h and omap850.h
ARM: OMAP2+: fix naming collision of variable nr_irqs
ARM: OMAP: omap2plus_defconfig: Enable EXT4 support
ARM: OMAP depends on MMU
arm: omap3: am35x: Set proper powerdomain states
ARM: OMAP AM35x: clockdomain data: Fix clockdomain dependencies
ARM: OMAP AM35x: EMAC/MDIO integration: Add Davinci EMAC/MDIO hwmod support
ARM: OMAP: AM35xx: fix UART4 softreset
ARM: OMAP AM35xx: clock and hwmod data: fix UART4 data
ARM: OMAP AM35xx: clock and hwmod data: fix AM35xx HSOTGUSB hwmod
ARM: OMAP: Fix dts files w/ status property: "disable" -> "disabled"
ARM: OMAP: beagle: Set USB Host Port 1 to OMAP_USBHS_PORT_MODE_UNUSED
ARM: OMAP2: twl-common: Fix compiler warning
ARM: OMAP: fix the ads7846 init code
mfd: twl: remove pdata->irq_base/_end, no more users
ARM: OMAP2+: TWL: remove usage of pdata->irq_base/_end
ARM: OMAP2+: OPP: Fix to ensure check of right oppdef after bad one
...
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A second batch of core patches for lpc32xx, based on top of the first
one in the lpc32xx-next branch.
* 'lpc32xx/core' of git://git.antcom.de/linux-2.6:
ARM: LPC32xx: Remove unused gpios
ARM: LPC32xx: Remove USB and I2C init from phy3250.c
ARM: LPC32xx: Cleanup USB clock init
ARM: LPC32xx: Remove wrong re-initialization of MMC clock register
ARM: LPC32xx: Add further bits to MMC init
ARM: LPC32xx: Init MMC via clock
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This branch contains device tree changes for lpc32xx that are
based on top of the earlier lpc32xx-next branch.
* 'lpc32xx/dts' of git://git.antcom.de/linux-2.6:
ARM: LPC32xx: Update DTS file for EA3250 board
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Device's regulator matches their hardware counterparts with the
property "regulator-compatible" of each child regulator node in
place of the child node name.
Add the property "regulator-compatible" for each regulator with
their hardware counterpart's name.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Add Variscite OMAP4 System-On-Modeule support
Signed-off-by: Uri Yosef <uri.y@variscite.com>
[tony@atomide.com: updated to use disabled instead of disable]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add AM335X BeagleBone device tree source (am335x-evm.dts) file
to use the am33xx.dtsi SoC file, along with the memory node
information.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Reviewed-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add AM335X EVM device tree source (am335x-evm.dts) file to
use the am33xx.dtsi SoC file, along with the memory node
information.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Reviewed-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add device tree source include file for the AM33XX SoC family.
An additional .dtsi file is created to describe the generic
AM33XX CPU module like intc, ocp.
Actual selection of available peripherals is handled in seperate
.dts files using this am33xx.dtsi generic header file.
Signed-off-by: AnilKumar Ch <anilkumar@ti.com>
Reviewed-by: Vaibhav Hiremath <hvaibhav@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add missing properties for fec, phy-supply, phy-reset-gpios and
phy-reset-duration, which are required by fec driver for successfully
probe fec from device tree, if bootloader hasn't set those things up.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add vmmc-supply for mmc device, so that the power to mmc slot can be
turned on by mmc driver if bootloader hasn't done it.
Also remove "okay" status for mmc1/ssp1, as the device has pin conflict
with gpmi-nand. Actually the device is already disabled since the
mxs-mmc driver adopts pinctrl support because there is no pinctrl setup
for the device in dts. Make this explicit by removing "okay" status.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The 8-bit mode mmc has pin conflicts with display. Let's use 4-bit
mode by default, so that display can be enabled together later.
Also add vmmc-supply for mmc device.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Before gpio_request can directly ask pinctrl system to configure the
requested pin into gpio mode, we use "hog" entry (pinctrl state of
pin controller itself) to configure gpios.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add comments for pinmux-ids so that we do not have to keep looking at
Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt to read
all these pinmux-ids.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use auxdata to attach mxsfb_platform_data for imx23-evk and imx28-evk.
We take this as a temporary solution for removing those board files,
and it should be updated to use common bindings for struct fb_videomode
when it becomes available.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
As the flexcan driver has DT binding for some time now. This patch makes
the flexcan driver available in the can drivers menu if a SOC with flexcan
is enabled.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The non-DT boot reads the mac from OTP and pass it to fec driver via
platform data. The patch provides an equivalent support for device
tree boot, with reading mac from OTP and store it in device tree,
and fec driver can get the mac from device tree at its probe time.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Replace "gpmi" with "gpmi-nand" to get the
GPMI interface probing with DT instead of
failing to get clock.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Detlev Zundel <dzu@denx.de>
CC: Dong Aisheng <b29396@freescale.com>
CC: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Linux ARM kernel <linux-arm-kernel@lists.infradead.org>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Wolfgang Denk <wd@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
add gpmi-nand device tree support.
add gpmi-nand pinctrl support.
Also enable the gpmi support for mx28-evk board.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Aas the flexcan driver has DT binding for some time now. This patch makes
the flexcan driver available in the can drivers menu if a SOC with flexcan
is enabled.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The recently added SDHI2 interface to kzm9g needs power supplies for the
upcoming transition away from OCR masks, provided in platform data.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
sh_clk_mstp32_register is deprecated. This convert to sh_clk_mstp_register.
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
From Shawn Guo <shawn.guo@linaro.org>, this makes it possible to use
sparse irqs with mach-imx.
* 'imx/sparse-irq' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: imx: enable SPARSE_IRQ for imx platform
ARM: fiq: change FIQ_START to a variable
tty: serial: imx: remove the use of MXC_INTERNAL_IRQS
ARM: imx: remove unneeded mach/irq.h inclusion
i2c: imx: remove unneeded mach/irqs.h inclusion
ARM: imx: add a legacy irqdomain for mx31ads
ARM: imx: add a legacy irqdomain for 3ds_debugboard
ARM: imx: pass gpio than irq number into mxc_expio_init
ARM: imx: leave irq_base of wm8350_platform_data uninitialized
dma: ipu: remove the use of ipu_platform_data
ARM: imx: move irq_domain_add_legacy call into avic driver
ARM: imx: move irq_domain_add_legacy call into tzic driver
gpio/mxc: move irq_domain_add_legacy call into gpio driver
ARM: imx: eliminate macro IRQ_GPIOx()
ARM: imx: eliminate macro IOMUX_TO_IRQ()
ARM: imx: eliminate macro IMX_GPIO_TO_IRQ()
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
A subsequent patch will add a generic PWM API driver for the Tegra PWFM
controller, supporting all four PWM devices with a single PWM chip. The
device will be named tegra-pwm and only one clock needs to be provided.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
PWM clock source registers in Tegra 2 have different clock source selection bit
fields than other registers. PWM clock source bits in CLK_SOURCE_PWM_0 register
are located at bit field bit[30:28] while others are at bit field bit[31:30] in
their respective clock source register.
This patch updates the clock programming to correctly reflect that, by adding a
flag to indicate the alternate bit field format and checking for it when
selecting a clock source (parent clock).
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
Signed-off-by: Simon Que <sque@chromium.org>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Move the driver to drivers/pwm/ and convert it to use the framework.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Alexey Charkov <alchark@gmail.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Move the driver to drivers/pwm/ and convert it to use the framework.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Kukjin Kim <kgene.kim@samsung.com>
[eric@eukrea.com: fix pwmchip_add return code test]
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Move the driver to drivers/pwm/ and convert it to use the framework.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[eric@eukrea.com: set chip.dev to prevent probe failure]
[eric@eukrea.com: fix pwmchip_add return code test]
Signed-off-by: Eric Bénard <eric@eukrea.com>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
This commit moves the PXA PWM driver to the drivers/pwm subdirectory and
converts it to use the new PWM framework.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Add auxdata to instantiate the PWFM controller from a device tree,
include the corresponding nodes in the dtsi files for Tegra 20 and
Tegra 30 and add binding documentation.
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
The number of lines of AIC5 has increased from 32 to 128. Due to this
increase, a source select register has been introduced for the interrupt
line selection. Moreover, register mapping has been changed. For that reasons,
we need some dedicated callbacks for AIC5.
Power management is also concerned by these changes. On suspend, we can't get
the whole interrupt mask register as before, we have to read this register 128
times. To reduce this overhead, a snapshot of the whole IMR is maintained.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
mach/irqs only defines FIQ_START which doesn't appear to be used anywhere
so remove it.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Enable sparse irq support for multisoc image. It involves to add the
NR_IRQS_LEGACY offset to static SoC irq number definitions since NR_IRQS_LEGACY
irq descs are allocated before AIC requests irq descs allocation.
Move NR_AIC_IRQS macro to a more appropiate place with the purpose to
remove mach/irqs.h later.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
SOC_AT91SAM9 selects MULTI_IRQ_HANDLER in order to let machines specify their
own IRQ handler at run time.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Since irq priorites are managed in DT, static ones are no more required for
sam9x5 which only has DT support.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add a third cell to define irq priority.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The Advanced Interrupt Controller allows us to use the fast EOI handler type.
It lets us remove the Atmel specific workaround into arch/arm/kernel/irq.c
used to indicate to the AIC the end of the interrupt treatment.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Commit 82c583e3ae ("AT91RM9200 hardware
headers") introduced arch/arm/mach-at91/include/mach/at91_spi.h and
arch/arm/mach-at91/include/mach/at91_ssc.h. (These files were called
at91rm9200_spi.h and at91rm9200_ssc.h then.) That commit was added in
the v2.6.18 development cycle.
Nothing includes them now and nothing uses the named constants they
provide. (There's no way these named constants could be used unless
these files were included somehow.) It actually seems these two headers
have never been used since they were added to the tree. They can safely
be removed.
Signed-off-by: Paul Bolle <pebolle@tiscali.nl>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
The SYS_NIRQ1 pin is the interupt line for the PMIC part of the TWL6030
and interrupts from the PMIC are needed as wakeup sources.
Ensure this pin is mux'd as input and has wakeup enabled so PMIC
interupts (e.g. RTC) can be used as wakeup sources.
Tested on OMAP4430/Panda.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
In order for suspend/resume dependencies to work correctly, I2C has to
be initialized (more specifically, registered with the driver core)
before MMC. Without this, the MMC driver fails to adjust the VMMC
regulator (using i2c writes) during the suspend path.
Problem found testing suspend/resume on 3730/OveroSTORM platform.
Signed-off-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Register the tvp5150 video decoder in ISP subsystem.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Setup pinmux for CPI and register the mt9t001 camera sensor
in ISP subsystem.
Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Register OMAP DRM/KMS platform device. DMM is split into a
separate device using hwmod.
Signed-off-by: Andy Gross <andy.gross@ti.com>
Signed-off-by: Rob Clark <rob.clark@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
commit 435ca24 (ARM i.MX: Visstrim_M10: Add board version detection)
included <asm/system.h>, which is a header file about to be deleted according to
9f97da (Disintegrate asm/system.h for ARM)
Include <asm/system_info.h> instead.
Reported-by: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
