This part just add necessary change to boot imx6ul.
Update clock and pinctrl for imx6ul
Signed-off-by: Frank Li <Frank.Li@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Extend the existing Vybrid eSDHC devicetree implementation to also
describe the esdhc0 functional block.
Tested on a custom VF610-based board with a Toshiba THGBM1G5D2EBAI7 eMMC
module attached to esdhc0.
Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.
Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.
With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit extends the existing Vybrid QSPI devicetree implementation
to also describe the qspi1 functional block.
Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Both 'reg' and 'reg-names' are required properties according to binding
documentation, and both should contain two items.
Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Freescale DSPI driver has been updated and supports TCF interrupt type now.
In the new driver we choose the interrupt type according the compatible
string of the device node.
This patch update the compatible string of DSPI device node of LS1021A in
order to use the correct interrupt type.
Signed-off-by: Haikun Wang <haikun.wang@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.
Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.
With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Gary Bisson <gary.bisson@boundarydevices.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.
Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.
With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Tested-by: Gary Bisson <gary.bisson@boundarydevices.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Warp board rev1.12 is the version of the hardware that will be publicly
available for the customers.
It uses UART5 as the Bluetooth serial port as well as some
additional signals for HOSTWAKE on Wifi and Bluetooth.
Make the changes to support the rev1.12 hardware.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Currently it is not possible to have HDMI and LVDS working simultaneously,
because both ports try to use PLL5.
Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be
driven from independent sources.
With this change the LDB pixel clock goes to 68.57 MHz, which is still
within the valid range for the HSD100PXN1 LVDS panel.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This is used as a base board for reference core modules.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Need the aon_pm_l2_intc and irq0_aon_intc descriptions, so included
those as well.
Signed-off-by: Gregory Fong <gregory.0xf0@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
In the default Broadcom SDK the shared override is activated for this
cache controller, do the same in the upstream code. Data and
instruction prefetching is not activated by default for this cache
controller on the bcm53xx SoC, do it manually like it is done in the
vendor SDK.
Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
some missed dt nodes or props for sirf dts for 4.3.
Among them:
- G2D
- PWM
- JPEG
- Multimedia
- PMU(performance monitor unit)
- GMAC
- SDR(software digital radio) and its DMA
- pinmux for NAND
- GPIO key
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Merge tag 'sirf-dts-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux into next/dt
ARM: sirf: dts update for 4.3
some missed dt nodes or props for sirf dts for 4.3.
Among them:
- G2D
- PWM
- JPEG
- Multimedia
- PMU(performance monitor unit)
- GMAC
- SDR(software digital radio) and its DMA
- pinmux for NAND
- GPIO key
* tag 'sirf-dts-for-4.3' of git://git.kernel.org/pub/scm/linux/kernel/git/baohua/linux:
ARM: dts: atlas7: add a GPIO key for rearview button
ARM: dts: atlas7: put pinctl property to get pinmux for NAND
ARM: dts: atlas7: add software digital radio nodes and its DMA channels
ARM: dts: atlas7: add lost PWM node
ARM: dts: atlas7: add lost G2D node
ARM: dts: atlas7: add multimedia codec node
ARM: dts: atlas7: add alias name for spi device
ARM: dts: atlas7: add lost gmac node
ARM: dts: atlas7: add performance monitor unit node
ARM: dts: atlas7: add lost jpeg node
Signed-off-by: Olof Johansson <olof@lixom.net>
Initial version of DTSI for ProXstream2 and PH1-LD6b and DTS for
PH1-LD6b reference board.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[olof: sort Makefile entries]
Signed-off-by: Olof Johansson <olof@lixom.net>
Initial version of UniPhier PH1-Pro5 device tree.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
- for exynos3250
: update video-phy node with syscon phandle
- for exynos4210
: add CPU OPP and regulator supply property
: use labels for overriding nodes for exynos4210-universal_c210
- for exynos4412-trats2
: set max17047 over heat and voltage thresholds
- for exynos5250 and 5420
: extend exynos5250/5420-pinctrl nodes using labels
: include exynos5250/5420-pinctrl after the nodes definitions
- for exynos5410-smdk5410
: clean up indentation
- for exynos5422-odroidxu3
: define default thermal-zones for exynos5422
: enable USB3 regulators, TMU and thermal-zones
: add pwm-fan node
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Merge tag 'samsung-dt-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
Samsung 1st DT updates for v4.3
- for exynos3250
: update video-phy node with syscon phandle
- for exynos4210
: add CPU OPP and regulator supply property
: use labels for overriding nodes for exynos4210-universal_c210
- for exynos4412-trats2
: set max17047 over heat and voltage thresholds
- for exynos5250 and 5420
: extend exynos5250/5420-pinctrl nodes using labels
: include exynos5250/5420-pinctrl after the nodes definitions
- for exynos5410-smdk5410
: clean up indentation
- for exynos5422-odroidxu3
: define default thermal-zones for exynos5422
: enable USB3 regulators, TMU and thermal-zones
: add pwm-fan node
* tag 'samsung-dt-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Extend exynos5420-pinctrl nodes using labels instead of paths
ARM: dts: Include exynos5420-pinctrl after the nodes were defined for exynos5420
ARM: dts: Extend exynos5250-pinctrl nodes using labels instead of paths
ARM: dts: Include exynos5250-pinctrl after the nodes were defined for exynos5250
ARM: dts: Enable thermal-zones for exynos5422-odroidxu3
ARM: dts: Define default thermal-zones for exynos5422
ARM: dts: Enable TMU for exynos5422-odroidxu3
ARM: dts: Add pwm-fan node for exynos5422-odroidxu3
ARM: dts: Use labels for overriding nodes for exynos4210-universal_c210
ARM: dts: Set max17047 over heat and voltage thresholds for exynos4412-trats2
ARM: dts: Enable USB3 regulators for exynos5422-odroidxu3
ARM: dts: Clean up indentation for exynos5410-smdk5410
ARM: dts: add CPU OPP and regulator supply property for exynos4210
ARM: dts: Update video-phy node with syscon phandle for exynos3250
Signed-off-by: Olof Johansson <olof@lixom.net>
The "altr,modrst-offset" property represents the offset into the reset manager
that is the first register to be used by the driver to bring peripherals out
of reset.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The reset manager for is pretty similar to the one for SoCFPGA
cyclone5/arria5 except for a few offsets. This patch adds those offsets.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Also known as the Asus Chromebook Flip.
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
The all current Rockchip SoCs supporting 4GB of ram have problems accessing
the memory region 0xfe000000~0xff000000. This also seems to includes the
rk3368 arm64 soc.
All current code handling dma memory oddities I could find, seem to involve
soc-specific code (zone-dma or so) while this issue is shared between arm32
and arm64 socs from Rockchip, which would need to have this described in
the soc devicetree on both socs.
Limiting the dma-zone alone also does not solve the issue and as the
dma-masks need to be a power-of-two in the kernel, the next lower dma-mask
brings memory usable for dma down to 2GB.
So as a stop-gap block off the affected region to prevent its use by
devices with 4GB of memory, like some recent Chromebooks.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
This enables the previously disabled usb controllers on the marsboard
and makes it possible to for example mount usb mass storage devices.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This adds the usbphy nodes to rk3066 and rk3188, which share the usb hosts
in rk3xxx.dtsi and also enables it on boards based around these socs.
The usb-phy itself is the same as used on the rk3288 already.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
According to the manual, the fifo sizes are the same as on later socs
like the rk3288 and this also fixes an error about "insufficient fifo
memory", as it seems the values read from the ip are wrong.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
The watchdog, the reset controller, the RTC, the shutdown controller, the
timer counters and the LCD PWM need the slow clock, add it to the currently
defined nodes.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The display module for at91sam9x5-ek has a few touch buttons, add support
for those.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Use the at91sam9x5 display module dtsi in the relevant board dts.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
All the at91sam9x5-ek share the share display module, add a dtsi to
describe it.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Actually make use of at91sam9x5_lcd.dtsi in the relevant SoC dtsis.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Define at91sam9x5 hlcdc node for the SoCs with an LCD controller.
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog, the reset controller, the RTC, the shutdown controller, the
timer counters and the LCD PWM need the slow clock, add it where necessary.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog, the reset controller, the RTC, the shutdown controller, the
timer counters and the LCD PWM need the slow clock, add it where necessary.
[boris.brezillon@free-electrons.com: add tcb clocks]
Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog, the reset controller, the RTC, the shutdown controller, the
timer counters and the LCD PWM need the slow clock, add it where necessary,
The LCD PWM will be handled later.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog, the reset controller, the RTC, the real-time timer, the
shutdown controller and the timer counter need the slow clock, add it where
necessary.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog, the reset controller, the RTC, the shutdown controller, the
timer counters and the LCD PWM need the slow clock, add it where necessary.
The LCD PWM will be handled later.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog, the reset controller, the RTC, the real-time timer, the
shutdown controller and the timer counters need the slow clock, add it
where necessary.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog, the reset controller, the two real-time timers, the shutdown
controller and the timer counter need the slow clock, add it where
necessary.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog, the reset controller, the real-time timer, the shutdown
controller and the timer counter need the slow clock, add it where
necessary.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog, the reset controller, the real-time timer, the shutdown
controller, the timer counters need the slow clock, add it where necessary.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The system timer, the RTC and the timer counters need the slow clock, add
it.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The RTC needs an input clock, it is the slow clock. It is required as it
will not function without it.
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
The watchdog has an input clock, the slow clock. It is required as it will
not function without it.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
