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Author SHA1 Message Date
Atsushi Nemoto
c59a0f15be [MIPS] Remove __flush_icache_page 
__flash_icache_page is unused, so kill it.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-10-01 23:16:58 +01:00
Ralf Baechle
a00f631018 [MIPS] c-r4k: Convert init functions from inline to __init. 
With more recent compilers inline doesn't necessarily means a function
will always be inlined.  So leave that decission to the compiler and
make the function as __init.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-09-27 13:37:44 +01:00
Atsushi Nemoto
f6502791d7 [MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache. 
c-r4k.c and c-sb1.c use drop_mmu_context() to flush virtually tagged
I-caches, but this does not work for flushing other task's icache.  This
is for example triggered by copy_to_user_page() called from ptrace(2).
Use indexed flush for such cases.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-09-27 13:37:37 +01:00
Ralf Baechle
585fa72493 [MIPS] Retire flush_icache_page from mm use. 
On the 34K the redundant cache operations were causing excessive stalls
resulting in realtime code running on the second VPE missing its deadline.
For all other platforms this patch is just a significant performance
improvment as illustrated by below benchmark numbers.

Processor, Processes - times in microseconds - smaller is better
------------------------------------------------------------------------------
Host                 OS  Mhz null null      open slct sig  sig  fork exec sh
                             call  I/O stat clos TCP  inst hndl proc proc proc
--------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
25Kf      2.6.18-rc4     533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K
25Kf      2.6.18-rc4-p   533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K
4Kc       2.6.18-rc4      80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K
4Kc       2.6.18-rc4-p    80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K
34Kc      2.6.18-rc4      40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K
34Kc      2.6.18-rc4-p    40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K
BCM1480   2.6.18-rc4     700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K
BCM1480   2.6.18-rc4-p   700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385
TX49-16K  2.6.18-rc3     197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K
TX49-16K  2.6.18-rc3-p   197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K
TX49-32K  2.6.18-rc3     396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K
TX49-32K  2.6.18-rc3-p   396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K
    
Original patch by me with enhancements by Atsushi Nemoto.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
 2006-09-27 13:37:34 +01:00
Ralf Baechle
df586d59a4 [MIPS] c-r4k: Typo fix. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-09-27 13:37:23 +01:00
Yoichi Yuasa
2874fe5533 [MIPS] vr41xx: Replace magic number for P4K bit with symbol. 
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-07-13 21:26:11 +01:00
Yoichi Yuasa
1058ecda9b [MIPS] vr41xx: Changed workaround to recommended method 
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-07-13 21:26:11 +01:00
Yoichi Yuasa
4e8ab36182 [MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80. 
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-07-13 21:26:06 +01:00
Ralf Baechle
fc5d2d279f [MIPS] Use the proper technical term for naming some of the cache macros. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-07-13 21:26:04 +01:00
Jörn Engel
6ab3d5624e Remove obsolete #include <linux/config.h> 
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
 2006-06-30 19:25:36 +02:00
Ralf Baechle
2e78ae3f48 [MIPS] 74K: Assume it will also have an AR bit in config7 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-06-29 21:10:54 +01:00
Ralf Baechle
beab375a48 [MIPS] Treat CPUs with AR bit as physically indexed. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-06-29 21:10:54 +01:00
Chris Dearman
73f403527b [MIPS] Fix handling of 0 length I & D caches. 
Don't ask.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-06-29 21:10:53 +01:00
Chris Dearman
9318c51acd [MIPS] MIPS32/MIPS64 secondary cache management 
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-06-29 21:10:52 +01:00
Sergei Shtylyov
9370b35175 [MIPS] Save write-only Config.OD from being clobbered 
Save the Config.OD bit from being clobbered by coherency_setup(). This
bit, when set, fixes various errata in the early steppings of Au1x00
SOCs.  Unfortunately, the bit was write-only on the most early of them.
In addition, also restore the bit after a wakeup from sleep.
    
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-06-06 00:15:13 +01:00
Kumba
44d921b246 [MIPS] Treat R14000 like R10000. 
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-06-01 00:28:35 +01:00
Ralf Baechle
7f3f1d01a9 [MIPS] Fix deadlock on MP with cache aliases. 
A proper fix would involve introducing the notion of shared caches but
at this stage of 2.6.17 that's going to be too intrusive and not needed
for current hardware; aside I think some discussion will be needed.

So for now on the affected SMP configurations which happen to suffer from
cache aliases we make use of the fact that a single cache will be shared
by all processors.  This solves the deadlock issue and will improve
performance by getting rid of the smp_call_function overhead.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-06-01 00:28:33 +01:00
Nigel Stephens
98a41de99a [MIPS] Add missing 34K processor IDs 
The 34K is very much like a 24K on steroids.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-06-01 00:28:30 +01:00
Atsushi Nemoto
3c68da798a [MIPS] Use __ffs() instead of ffs() for waybit calculation. 
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-04-19 04:14:30 +02:00
Ralf Baechle
7e3bfc7cfc [MIPS] Handle IDE PIO cache aliases on SMP. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-04-19 04:14:29 +02:00
Atsushi Nemoto
67a3f6de93 [MIPS] Fix tx49_blast_icache32_page_indexed. 
Fix the cache index value in tx49_blast_icache32_page_indexed().
This is a damage by de62893bc0 commit.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-04-19 04:14:21 +02:00
Atsushi Nemoto
de862b488e [MIPS] TX49XX has prefetch. 
The TX49XX has the prefetch instruction.  It supports only Pref_Load
(hint 0).  Actually changes in this patch except for Kconfig are not
have any effects, I added these changes to prevent misuse of unsupported
hints.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-03-21 13:27:47 +00:00
Atsushi Nemoto
de62893bc0 [MIPS] local_r4k_flush_cache_page fix 
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly.  Make
blast_?cache_page_indexed() masks its index value correctly.  Also,
use physical address for physically indexed pcache/scache.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-03-18 16:59:27 +00:00
Ralf Baechle
4debe4f963 [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs. 
When a CPU has no scache, the scache flushing functions currently
aren't getting initialized and the NULL pointer is eventually called
as a function.  Initialize the scache flushing functions as a noop
when there's no scache.
    
Initial patch by me and most of the debugging done by Martin Michlmayr.
    
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-02-28 17:04:19 +00:00
Atsushi Nemoto
41700e7399 [MIPS] Add protected_blast_icache_range, blast_icache_range, etc. 
Add blast_xxx_range(), protected_blast_xxx_range() etc. for common
use.  They are built by __BUILD_BLAST_CACHE_RANGE().
Use protected_cache_op() macro for various protected_ routines.
Output code should be logically same.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-02-14 19:13:24 +00:00
Atsushi Nemoto
d4264f1839 [MIPS] Remove wrong __user tags. 
This fixes sparse warnings 'dereference of noderef expression'.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-02-07 13:30:25 +00:00
Ralf Baechle
e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-01-10 13:39:06 +00:00
Ralf Baechle
6ec25809c1 Rename page argument of flush_cache_page to something more descriptive. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:42 +01:00
Ralf Baechle
02cf211968 Cleanup the mess in cpu_cache_init. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:32 +01:00
Thiemo Seufer
10a3dabddd Add/Fix missing bit of R4600 hit cacheop workaround. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:18 +01:00
Thiemo Seufer
02fe2c9ce3 Minor code cleanup. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:17 +01:00
Thiemo Seufer
d8748a3abf More .set push/pop. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:16 +01:00
Thiemo Seufer
330cfe016b Let r4600 PRID detection match only legacy CPUs, cleanups. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:32:15 +01:00
Ralf Baechle
1d40cfcd34 Avoid SMP cacheflushes. This is a minor optimization of startup but 
will also avoid smp_call_function from doing stupid things when called
from a CPU that is not yet marked online.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:54 +01:00
Ralf Baechle
e01402b115 More AP / SP bits for the 34K, the Malta bits and things. Still wants 
a little polishing.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:53 +01:00
Ralf Baechle
ec74e361f1 Mark a few variables __read_mostly. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:46 +01:00
Ralf Baechle
cc61c1fede MIPS R2 instruction hazard handling. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:46 +01:00
Thiemo Seufer
ba5187dbb4 Better interface to run uncached cache setup code. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:31:11 +01:00
Ralf Baechle
fe00f943e0 Sparseify MIPS. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:50 +01:00
Pete Popov
e3ad1c23ba Base Au1200 2.6 support. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:47 +01:00
Thiemo Seufer
26a51b270f Use intermediate variable. 
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:38 +01:00
Ralf Baechle
79acf83e50 Moves a test which determines if we actually need to perform a 
cacheflush to the right place.  That's a bug which is harmless on UP
but a severe bug on SMP.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:31 +01:00
Ralf Baechle
c6e8b58771 Update MIPS to use the 4-level pagetable code thereby getting rid of 
the compacrapability headers.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:31 +01:00
Ralf Baechle
505403b6a0 25Kf is also physically indexed. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:29 +01:00
Ralf Baechle
a95970f323 20Kc and SB1 don't suffer from aliases. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:28 +01:00
Ralf Baechle
ae6aafe309 Move missplaced code line to the right place. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:26 +01:00
Ralf Baechle
d1e344e500 Use hardware mechanism to deal with cache aliases in the 24K. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:25 +01:00
Ralf Baechle
28ecca4786 Remove old wrong bits of cache code. 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2005-10-29 19:30:25 +01:00
Ralf Baechle
42a3b4f25a [PATCH] mips: nuke trailing whitespace 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
 2005-09-05 00:06:07 -07:00
Ralf Baechle
875d43e72b [PATCH] mips: clean up 32/64-bit configuration 
Start cleaning 32-bit vs. 64-bit configuration.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
 2005-09-05 00:06:06 -07:00