move the init sections to the end of memory, so that after they
are free, run time memory is all continugous - this should help decrease
memory fragementation. When doing this, we also pack some of the other
sections a little closer together, to make sure we don't waste memory.
To make this happen, we need to rename the .data.init_task section to
.init_task.data, so it doesn't get picked up by the linker script glob.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Remove some sort of bloaty code, try to get these pin_req arrays built at compile-time
- move this static things to the blackfin board file
- add pin_req array to struct bfin5xx_spi_master
- tested on BF537/BF548 with SPI flash
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
We currently do not. Also make it easier to handle cplb violations - in traps.c
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Simplify "make ARCH=x86" and fix kconfig so we again
can set 64BIT in all.config.
For a fix the diffstat is nice:
6 files changed, 3 insertions(+), 36 deletions(-)
The patch reverts these commits:
0f855aa64b
-> kconfig: add helper to set config symbol from environment variable
2a113281f5
-> kconfig: use $K64BIT to set 64BIT with all*config targets
Roman Zippel pointed out that kconfig supported string
compares so the additional complexity introduced by the
above two patches were not needed.
With this patch we have following behaviour:
# make {allno,allyes,allmod,rand}config [ARCH=...]
option \ host arch | 32bit | 64bit
=====================================================
./. | 32bit | 64bit
ARCH=x86 | 32bit | 32bit
ARCH=i386 | 32bit | 32bit
ARCH=x86_64 | 64bit | 64bit
The general rule are that ARCH= and native architecture
takes precedence over the configuration.
So make ARCH=i386 [whatever] will always build a 32-bit
kernel no matter what the configuration says.
The configuration will be updated to 32-bit if it was
configured to 64-bit and the other way around.
This behaviour is consistent with previous behaviour so
no suprises here.
make ARCH=x86 will per default result in a 32-bit kernel
but as the only ARCH= value x86 allow the user to select
between 32-bit and 64-bit using menuconfig.
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Cc: Roman Zippel <zippel@linux-m68k.org>
Cc: Andreas Herrmann <aherrman@arcor.de>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Needed to make the wireless board, WRAP2C reboot.
Cc: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
need to check info->res_num less than PCI_BUS_NUM_RESOURCES, so
info->bus->resource[info->res_num] = res will not beyond of bus resource
array when acpi returns too many resource entries.
Signed-off-by: Yinghai Lu <yinghai.lu@sun.com>
Cc: Greg Kroah-Hartman <gregkh@suse.de>
Cc: Gary Hade <gary.hade@us.ibm.com>
Cc: Len Brown <lenb@kernel.org>
Cc: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Some BIOSes advertise HPET at 0x0. We really do no want to
allocate a resource there. Check for it and leave early.
Other BIOSes tell us the HPET is at 0xfed0000000000000
instead of 0xfed00000. Add a check and fix it up with a warning
on user request.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Correct potentially unstable PC RTC time register reading in time_64.c
Stop the use of an incorrect technique for reading the standard PC RTC
timer, which is documented to "disconnect" time registers from the bus
while updates are in progress. The use of UIP flag while interrupts
are disabled to protect a 244 microsecond window is one of the
Motorola spec sheet's documented ways to read the RTC time registers
reliably.
tglx: removed locking changes from original patch, as they gain nothing
(read_persistent_clock is only called during boot, suspend, resume - so
no hot path affected) and conflict with the paravirt locking scheme
(see 32bit code), which we do not want to complicate for no benefit.
Signed-off-by: David P. Reed <dpreed@reed.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Fix hard freeze on x86_64 when the ntpd service calls
update_persistent_clock()
A repeatable but randomly timed freeze has been happening in Fedora 6
and 7 for the last year, whenever I run the ntpd service on my AMD64x2
HP Pavilion dv9000z laptop. This freeze is due to the use of
spin_lock(&rtc_lock) under the assumption (per a bad comment) that
set_rtc_mmss is called only with interrupts disabled. The call from
ntp.c to update_persistent_clock is made with interrupts enabled.
Signed-off-by: David P. Reed <dpreed@reed.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
92cb7612ae sets cpu_info->cpu_index to zero
for no reason. Referencing cpu_info->cpu_index now points always to CPU#0,
which is apparently not what we want.
Remove it.
Spotted-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Fix regressions introduced with 92cb7612ae.
It can happen that cpuinfo is displayed for CPUs that are not online or
even worse for CPUs not present at all. As an example, following was
shown for a "second" CPU of a single core K8 variant:
processor : 0
vendor_id : unknown
cpu family : 0
model : 0
model name : unknown
stepping : 0
cache size : 0 KB
fpu : yes
fpu_exception : yes
cpuid level : 0
wp : yes
flags :
bogomips : 0.00
clflush size : 0
cache_alignment : 0
address sizes : 0 bits physical, 0 bits virtual
power management:
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Commit d435d862ba
("cpu hotplug: mce: fix cpu hotplug error handling")
changed the error handling in mce_cpu_callback.
In cases where not all CPUs are brought up during
boot (e.g. using maxcpus and additional_cpus parameters)
mce_cpu_callback now returns NOTFIY_BAD because
for such CPUs cpu_data is not completely filled when
the notifier is called. Thus mce_create_device fails right
at its beginning:
if (!mce_available(&cpu_data[cpu]))
return -EIO;
As a quick fix I suggest to check boot_cpu_data for MCE.
To reproduce this regression:
(1) boot with maxcpus=2 addtional_cpus=2 on a 4 CPU x86-64 system
(2) # echo 1 >/sys/devices/system/cpu/cpu2/online
-bash: echo: write error: Invalid argument
dmesg shows:
_cpu_up: attempt to bring up CPU 2 failed
Signed-off-by: Andreas Herrmann <andreas.herrmann3@amd.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
dont use the vgetcpu tcache - it's causing problems with tasks
migrating, they'll see the old cache up to a jiffy after the
migration, further increasing the costs of the migration.
In the worst case they see a complete bogus information from
the tcache, when a sys_getcpu() call "invalidated" the cache
info by incrementing the jiffies _and_ the cpuid info in the
cache and the following vdso_getcpu() call happens after
vdso_jiffies have been incremented.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Ulrich Drepper <drepper@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Fix Voyager section mismatch due to using __devinit instead of __cpuinit.
WARNING: vmlinux.o(.text+0xd943): Section mismatch: reference to .init.text:init_gdt (between 'voyager_smp_prepare_boot_cpu' and 'smp_vic_cmn_interrupt')
Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] 4638/1: pxa: use PXA3xx specific macros to define clks
[ARM] remove useless setting of VM_RESERVED
PXA3xx uses its own clk_pxa3xx_cken_ops, modify the code to use the
PXA3xx specific macros to define its clocks
Signed-off-by: eric miao <eric.miao@marvell.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] N32 needs to use the compat version of sys_nfsservctl.
[MIPS] irq_cpu: use handle_percpu_irq handler to avoid dropping interrupts.
[MIPS] Sibyte: Fix name of clocksource.
[MIPS] SNI: s/achknowledge/acknowledge/
[MIPS] Makefile: Fix canonical system names
[MIPS] vpe: handle halting TCs in an errata safe way.
[MIPS] Sibyte: Stop timers before programming next even.
[MIPS] Sibyte: Increase minimum oneshot timer interval to two ticks.
[MIPS] Lasat: Fix overlap of interrupt number ranges.
[MIPS] SNI PCIT CPLUS: workaround for b0rked irq wiring of onboard PCI bus 1
[MIPS] Fix shadow register support.
[MIPS] Change get_cycles to always return 0.
[MIPS] Fix typo in R3000 TRACE_IRQFLAGS code
[MIPS] Sibyte: Replace use of removed IO_SPACE_BASE with IOADDR.
[MIPS] iounmap if in vr41xx_pciu_init() pci clock is over 33MHz
[MIPS] BCM1480: Remove duplicate acknowledge of timer interrupt.
[MIPS] Sibyte: pin timer interrupt to their cores.
[MIPS] Qemu: Add early printk, your friend in a cold night.
[MIPS] Convert reference to mem_map to pfn_to_page().
[MIPS] Sibyte: resurrect old cache hack.
This matters to any sort of device that is wired to one of the CPU
interrupt pins on an SMP system. Typically the scenario is most easily
triggered with the count/compare timer interrupt where the same interrupt
number and thus irq_desc is used on each processor.
CPU A CPU B
do_IRQ()
generic_handle_irq()
handle_level_irq()
spin_lock(desc_lock)
set IRQ_INPROGRESS
spin_unlock(desc_lock)
do_IRQ()
generic_handle_irq()
handle_level_irq()
spin_lock(desc_lock)
IRQ_INPROGRESS set => bail out
spin_lock(desc_lock)
clear IRQ_INPROGRESS
spin_unlock(desc_lock)
In case of the cp0 compare interrupt this means the interrupt will be
acked and not handled or re-armed on CPU b, so there won't be any timer
interrupt until the count register wraps around.
With kernels 2.6.20 ... 2.6.23 we usually were lucky that things were just
working right on VSMP because the count registers are synchronized on
bootup so it takes something that disables interrupts for a long time on
one processor to trigger this one.
For scenarios where an interrupt is multicasted or broadcasted over several
CPUs the existing code was safe and the fix will break it. There is no
way to know in the interrupt controller code because it is abstracted from
the platform code. I think we do not have such a setup currently, so this
should be ok.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The GNU `config.guess' uses "linux-gnu" as the canonical system name.
Fix the list of compiler prefixes checked to spell it correctly.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Adds a JR.HB after halting a TC, to ensure that the TC has really halted.
only modifies the TCSTATUS register when the TC is safely halted.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We have no guarantee by the generic time code that the timer is stopped
when the ->next_event method is called. Modifying the Timer Initial Count
register while the timer is enabled has UNPREDICTABLE effect according to
the BCM1250/BCM1125/BCM1125H User Manual. So stop the timer before
reprogramming.
This is a paranoia fix; no ill effects have been observed previously.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
For the old minimum of a single tick a value of zero would be programmed
into the init value register which in the BCM1250/BCM1125/BCM1125H User
Manual in the Timer Special Cases section is documented to have
UNPREDICTABLE effect.
Observable sympthoms of this bug were hangs of several seconds on the
console during bootup and later if both dyntick and highres timer options
were activated.
In theory contiguous mode of the timers is also affected but in an act of
hopeless lack of realism I'll assume nobody will ever configure a KERNEL
for HZ > 500kHz but if so I leave that to evolution to sort out.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The range of MIPS_CPU IRQ and the range of LASAT IRQ overlap.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Shadow register support would not possibly have worked on multicore
systems. The support code for it was also depending not on MIPS R2 but
VSMP or SMTC kernels even though it makes perfect sense with UP kernels.
SR sets are a scarce resource and the expected usage pattern is that
users actually hardcode the register set numbers in their code. So fix
the allocator by ditching it. Move the remaining CPU probe bits into
the generic CPU probe.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
iounmap if pci clock is over 33MHz. Cosmetic because the iomap() in this
case is just a bit of address magic.
Signed-off-by: Roel Kluin <12o3l@tiscali.nl>
Acked-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The recent switch of the Sibyte SOCs from the processor specific cache
managment code in c-sb1.c to c-r4k.c lost this old hack
[MIPS] Hack for SB1 cache issues
Removing flush_icache_page a while ago broke SB1 which was using an empty
flush_data_cache_page function. This glues things well enough so a more
efficient but also more intrusive solution can be found later.
Signed-Off-By: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
in the hope it was no longer needed. As it turns it still is so resurrect
it until there is a better solution.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Oprofile needs to call intc_get_pending() in order to determine
whether a performance counter interrupt is pending.
Also, include the header which declares intc_get_pending() and fix the
definition to match the prototype.
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
There's a duplicate clock index between USART0 and USART1 which may be
causing system crashes when USART0 is used. Change the USART0 index
to '3', indicating the clock that is actually used by USART0.
Signed-off-by: Ben Nizette <ben@niasdigital.com>
Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
