Commit graph

11230 commits

Author SHA1 Message Date
Alex Deucher 072b5acc7e drm/radeon: implement bo copy callback using CP DMA (v2)
Lighter weight than using the 3D engine.

v2: fix ring count

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14 10:11:26 -04:00
Alex Deucher aeea40cbf9 drm/radeon: Disable dma rings for bo moves on r6xx
They still seem to cause instability on some r6xx parts.
As a follow up, we can switch to using CP DMA for bo
moves on r6xx as a lighter weight alternative to using
the 3D engine.

A version of this patch should also go to stable kernels.

Tested-by: J.N. <golden.fleeced@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14 10:11:25 -04:00
Alex Deucher 9847b36af4 drm/radeon/dpm: disable gfx PG on PALM
Gfx PG doesn't seem to work properly when UVD is initialized
on certain PALM boards.  Disable gfx PG for now until we sort
out a proper fix.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-14 10:11:24 -04:00
Alex Deucher c2b4cacfe9 drm/radeon/hdmi: make sure we have an afmt block assigned
Prevents a segfault if an afmt block is not assigned to the
encoder such as in the LVDS or eDP case.

Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=66714

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2013-07-14 10:10:53 -04:00
Stéphane Marchesin bcf53de4e6 drm/i915: Preserve the DDI_A_4_LANES bit from the bios
Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes
on eDP. This fixes eDP on hsw with > 2 lanes.

Also s/port_reversal/saved_port_bits/ since the current name is
confusing.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-13 10:44:32 +02:00
Daniel Vetter 21d8a4756a drm/i915: fix pfit regression for non-autoscaled resolutions
I.e. for letter/pillarboxing. For those cases we need to adjust the
mode a bit, but Jesse gmch pfit refactoring in

commit 2dd24552ca
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Thu Apr 25 12:55:01 2013 -0700

    drm/i915: factor out GMCH panel fitting code and use for eDP v3

broke that by reordering the computation of the gmch pfit state with
the block of code that prepared the adjusted mode for it and told the
modeset core not to overwrite the adjusted mode with default settings.

We might want to switch around the core code to just fill in defaults,
but this code predates the pipe_config modeset rework. And in the old
crtc helpers we did not have a suitable spot to do this.

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Hans de Bruin <jmdebruin@xmsnet.nl>
Reported-and-tested-by: Hans de Bruin <jmdebruin@xmsnet.nl>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-12 18:55:08 +02:00
Daniel Vetter 50b44a449f drm/i915: clear DPLL reg when disabling i9xx dplls
Toghether with the hw state readout this should catch cases where we
don't properly updated the pll state (either in sw or hw). At least
for the shared dpll code the equivalent tricke helped a lot in
catching bugs.

Also rename the function prefix, it's not a generic piece of
infrastructure.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-12 18:54:02 +02:00
Daniel Vetter 3ad8a208ab drm/i915: Fix up cpt pixel multiplier enable sequence
Bspec for the "DPLL HDMI multiplier" field says:

"Restriction : The DPLL must be enabled and stable before setting these bits.
These bits must be programmed after DPLL_SEL is programmed."

There is apparently no restriction on programming the DPLL_SEL
register wrt the DPLL. So let's just move that up before we enable the
pch dpll.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-12 18:54:01 +02:00
Daniel Vetter 426115cf5d drm/i915: clean up vlv ->pre_pll_enable and pll enable sequence
No need to call the ->pre_pll_enable hook twice if we don't enable the
dpll too early. This should make Jani a bit less grumpy.

v2: Rebase on top of the newly-colored BUG_ONs.

v3: Reinstate the lost write of the DPLL_MD register, spotted by Imre.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-12 18:54:01 +02:00
Mika Kuoppala 84734a049d drm/i915: move error state to own compilation unit
Move error state generation and stringification to it's
own compilation unit. Sysfs also uses this so it can't be
under CONFIG_DEBUG_FS

This fixes a regression introduced in

commit ef86ddced7
Author: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Date:   Thu Jun 6 17:38:54 2013 +0300

    drm/i915: add error_state sysfs entry

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66814
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-12 18:53:13 +02:00
Damien Lespiau 53b9140849 drm/i915: Don't attempt to read an unitialized stack value
If intel_sdvo_get_value() fails here, val is unitialized and the cross
check will compare the pipe config multiplier with a bogus value.

Instead, only set encoder_pixel_multiplier when the sdvo command has
been successful. The cross check will compare the pipe config value with
0 otherwise.

v2: Do the cross check with the initial value of encoder_pixel_multiplier (0)
if the sdvo command fails (and thus keep the warning) (Daniel Vetter)

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-12 17:33:21 +02:00
Damien Lespiau 08e2a7de8e drm/i915: Use for_each_pipe() when possible
Came accross two open coding of for_each_pipe(), might as well use the
macro.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 21:53:10 +02:00
Daniel Vetter 0692282181 drm/i915: fix up readout of the lvds dither bit on gen2/3
It's in the PFIT_CONTROL register, but very much associated with the
lvds encoder. So move the readout for it (in the case of an otherwise
disabled pfit) from the pipe to the lvds encoder's get_config
function.

Otherwise we get a pipe state mismatch if we use pipe B for a non-lvds
output and we've left the dither bit enabled behind us. This can
happen if the BIOS has set the bit (some seem to unconditionally do
that, even in the complete absence of an lvds port), but not enabled
pipe B at boot-up. Then we won't clear the pfit control register since
we can only touch that if the pfit is associated with our pipe in the
crtc configuration - we could trample over the pfit state of the other
pipe otherwise since it's shared. Once pipe B is enabled we notice
that the 6to8 dither bit is set and complain about the mismatch.

Note that testing indicates that we don't actually need to set this
bit when the pfit is disabled, dithering on 18bpp panels seems to work
regardless. But ripping that code out is not something for a bugfix
meant for -rc kernels.

v2: While at it clarify the logic in i9xx_get_pfit_config, spurred by
comments from Chris on irc.

v3: Use Chris suggestion to make the control flow in
i9xx_get_pfit_config easier to understand.

v4: Kill the extra line, spotted by Chris.

Reported-by: Knut Petersen <Knut_Petersen@t-online.de>
Cc: Knut Petersen <Knut_Petersen@t-online.de>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
References: http://lists.freedesktop.org/archives/intel-gfx/2013-July/030092.html
Tested-by: Knut Petersen <Knut_Petersen@t-online.de>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 19:21:27 +02:00
Daniel Vetter c0d6a3dd61 drm/i915: don't enable PM_VEBOX_CS_ERROR_INTERRUPT
The code to handle it is broken - there's simply no code to clear CS
parser errors on gen5+. And behold, for all the other rings we also
don't enable it!

Leave the handling code itself in place just to be consistent with the
existing mess though. And in case someone feels like fixing it all up.

This has been errornously enabled in

commit 12638c57f3
Author: Ben Widawsky <ben@bwidawsk.net>
Date:   Tue May 28 19:22:31 2013 -0700

    drm/i915: Enable vebox interrupts

Cc: Damien Lespiau <damien.lespiau@intel.com>
Cc: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:37:00 +02:00
Daniel Vetter c7113cc35f drm/i915: unify ring irq refcounts (again)
With the simplified locking there's no reason any more to keep the
refcounts seperate.

v2: Readd the lost comment that ring->irq_refcount is protected by
dev_priv->irq_lock.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:36:49 +02:00
Daniel Vetter 59cdb63d52 drm/i915: kill dev_priv->rps.lock
Now that the rps interrupt locking isn't clearly separated (at elast
conceptually) from all the other interrupt locking having a different
lock stopped making sense: It protects much more than just the rps
workqueue it started out with. But with the addition of VECS the
separation started to blurr and resulted in some more complex locking
for the ring interrupt refcount.

With this we can (again) unifiy the ringbuffer irq refcounts without
causing a massive confusion, but that's for the next patch.

v2: Explain better why the rps.lock once made sense and why no longer,
requested by Ben.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:36:43 +02:00
Daniel Vetter 2adbee62e0 drm/i915: queue work outside spinlock in hsw_pm_irq_handler
And kill the comment about it. Queueing work is a barrier type event,
no amount of locking will help in ordering things (as long as we queue
the work after having updated all relevant data structures). Also, the
queue_work works itself as a sufficient memory barrier.

Again on the surface this is just a tiny micro-optimization to reduce
the hold-time of dev_priv->irq_lock. But the better reason is that it
reduces superficial locking and so makes it clearer what we actually
need for correctness.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:36:34 +02:00
Daniel Vetter 41a05a3a5c drm/i915: streamline hsw_pm_irq_handler
The if (pm_iir & ~GEN6_PM_RPS_EVENTS) check was redunandant. Otoh
adding a check for rps events allows us to avoid the spinlock grabbing
for VECS interrupts.

v2: Drop misplaced hunk which now moved to the right patch.

Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:36:23 +02:00
Daniel Vetter d0ecd7e221 drm/i915: irq handlers don't need interrupt-safe spinlocks
Since we only have one interrupt handler and interrupt handlers are
non-reentrant.

To drive the point really home give them all an _irq_handler suffix.

This is a tiny micro-optimization but even more important it makes it
clearer what locking we actually need. And in case someone screws this
up: lockdep will catch hardirq vs. other context deadlocks.

v2: Fix up compile fail.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:36:13 +02:00
Daniel Vetter de28075d5b drm/i915: kill lpt pch transcoder->crtc mapping code for fifo underruns
It's racy: There's no guarantee that we won't walk this code (due to a
pch fifo underrun interrupt) while someone is changing the pointers
around.

The only reason we do this is to use the righ crtc for the pch fifo
underrun accounting. But we never expose this to userspace, so
essentially no one really cares if we use the "wrong" crtc.

So let's just rip it out.

With this patch fifo underrun code will always use crtc A for tracking
underruns on the (only) pch transcoder on LPT.

v2: Add a big comment explaining what's going on. Requested by Paulo.

v3: Fixup spelling in comment as spotted by Paulo.

Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:36:02 +02:00
Daniel Vetter 7336df6512 drm/i915: improve GEN7_ERR_INT clearing for fifo underrun reporting
Same treatment as for SERR_INT: If we clear only the bit for the pipe
we're enabling (but unconditionally) then we can always check for
possible underruns after having disabled the interrupt. That way pipe
underruns won't be lost, but at worst only get reported in a delayed
fashion.

v2: The same logic bug as in the SERR handling change also existed
here. The same bugfix of only reporting missed underruns when the
error interrupt was masked applies, too.

v3: Do the same fixes as for the SERR handling that Paulo suggested in
his review:
- s/%i/%c/ fix in the debug output
- move the DE_ERR_INT_IVB read into the respective if block

Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Fix up the checkpatch bikeshed Paulo noticed.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:35:48 +02:00
Daniel Vetter 1dd246fb16 drm/i915: improve SERR_INT clearing for fifo underrun reporting
The current code won't report any fifo underruns on cpt if just one
pipe has fifo underrun reporting disabled. We can't enable the
interrupts, but we can still check the per-transcoder bits and so
report the underrun delayed if:
- We always clear the transcoder's bit (and none of the other bits)
  when enabling.
- We check the transcoder's bit after disabling (to avoid racing with
  the interrupt handler).

v2: I've forgotten to actually remove the old SERR_INT clearing.

v3: Use transcoder_name as suggested by Paulo Zanoni. Paulo also
noticed a logic bug: When an underrun interrupt fires we report it
both in the interrupt handler and when checking for underruns when
disabling it in cpt_set_fifo_underrun_reporting. But that second check
is only required if the interrupt is disabled and we're switching of
underrun reporting (e.g. because we're disabling the crtc). Hence
check for that condition.

At first I wanted to rework the code to pass that bit of information
from the uppper functions down to cpt_set_fifo_underrun_reporting. But
that turned out too messy. Hence the quick&dirty check whether the
south error interrupt source is masked off or not.

v4: Streamline the control flow a bit.

v5: s/pipe/pch transcoder/ in the dmesg output, suggested by Paulo.

v6: Review from Paulo:
- Reorder the was_enabled assignment to only read the register when we
  need it. Also add a comment that we need to do that before updating
  the register.
- s/%i/%c/ fix for the debug output.
- Fix the checkpath complaint in the SERR_INT_TRANS_FIFO_UNDERRUN
  #define.

v7: Hopefully put that elusive SERR hunk back into this patch, spotted
by Paulo.

Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:34:32 +02:00
Daniel Vetter fee884ed28 drm/i915: extract ibx_display_interrupt_update
This way all changes to SDEIMR all go through the same function, with
the exception of the (single-threaded) setup/teardown code.

For paranoia again add an assert_spin_locked.

v2: For even more paranoia also sprinkle a spinlock assert over
cpt_can_enable_serr_int since we need to have that one there, too.

v3: Fix the logic of interrupt enabling, add enable/disable macros for
the simple cases in the fifo code and add a comment. All requested by
Paulo.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-11 14:34:06 +02:00
Linus Torvalds 496fd15bee drm: avoid warning in drm_load_edid_firmware()
Use "const char *" instead of "char *" in order to avoid this warning:

  drivers/gpu/drm/drm_edid_load.c: In function ‘drm_load_edid_firmware’:
  drivers/gpu/drm/drm_edid_load.c:245:25: warning: initialization discards ‘const’ qualifier from pointer target type [enabled by default]

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-07-10 14:21:46 -07:00
Chris Wilson 46a0b638f3 Revert "drm/i915: Workaround incoherence between fences and LLC across multiple CPUs"
This reverts commit 25ff119 and the follow on for Valleyview commit 2dc8aae.

commit 25ff1195f8
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Thu Apr 4 21:31:03 2013 +0100

    drm/i915: Workaround incoherence between fences and LLC across multiple CPUs

commit 2dc8aae06d
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Wed May 22 17:08:06 2013 +0100

    drm/i915: Workaround incoherence with fence updates on Valleyview

Jon Bloomfield came up with a plausible explanation and cheap fix
(drm/i915: Fix incoherence with fence updates on Sandybridge+) for the
race condition, so lets run with it.

This is a candidate for stable as the old workaround incurs a
significant cost (calling wbinvd on all CPUs before performing the
register write) for some workloads as noted by Carsten Emde.

Link: http://lists.freedesktop.org/archives/intel-gfx/2013-June/028819.html
References: https://www.osadl.org/?id=1543#c7602
References: https://bugs.freedesktop.org/show_bug.cgi?id=63825
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Cc: Carsten Emde <C.Emde@osadl.org>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-10 15:31:12 +02:00
Maarten Lankhorst 12f56f5192 drm/i915: remove unused members from drm_i915_private
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-10 14:57:06 +02:00
Chris Wilson d18b961903 drm/i915: Fix incoherence with fence updates on Sandybridge+
This hopefully fixes the root cause behind the workaround added in

commit 25ff1195f8
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Thu Apr 4 21:31:03 2013 +0100

    drm/i915: Workaround incoherence between fences and LLC across multiple CPUs

Thanks to further investigation by Jon Bloomfield, he realised that
the 64-bit register might be broken up by the hardware into two 32-bit
writes (a problem we have encountered elsewhere). This non-atomicity
would then cause an issue where a second thread would see an
intermediate register state (new high dword, old low dword), and this
register would randomly be used in preference to its own thread register.
This would cause the second thread to read from and write into a fairly
random tiled location.  Breaking the operation into 3 explicit 32-bit
updates (first disable the fence, poke the upper bits, then poke the lower
bits and enable) ensures that, given proper serialisation between the
32-bit register write and the memory transfer, that the fence value is
always consistent.

Armed with this knowledge, we can explain how the previous workaround
work. The key to the corruption is that a second thread sees an
erroneous fence register that conflicts and overrides its own. By
serialising the fence update across all CPUs, we have a small window
where no GTT access is occurring and so hide the potential corruption.
This also leads to the conclusion that the earlier workaround was
incomplete.

v2: Be overly paranoid about the order in which fence updates become
visible to the GPU to make really sure that we turn the fence off before
doing the update, and then only switch the fence on afterwards.

Signed-off-by: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Carsten Emde <C.Emde@osadl.org>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-10 14:41:46 +02:00
Daniel Vetter db1b76ca6a drm/i915: don't frob mm.suspended when not using ums
In kernel modeset driver mode we're in full control of the chip,
always. So there's no need at all to set mm.suspended in
i915_gem_idle. Hence move that out into the leavevt ioctl. Since
i915_gem_idle doesn't suspend gem any more we can also drop the
re-enabling for KMS in the thaw function.

Also clean up the handling of mm.suspend at driver load by coalescing
all the assignments.

Stumbled over while reading through our resume code for unrelated
reasons.

v2: Shovel mm.suspended into the (newly created) ums dungeon as
suggested by Chris Wilson. The plan is that once we've completely
stopped relying on the register save/restore code we could shovel even
that in there.

v3: Improve the locking for the entervt/leavevt ioctls a bit by moving
the dev->struct_mutex locking outside of i915_gem_idle. Also don't
clear dev_priv->ums.mm_suspended for the kms case, we allocate it with
kzalloc. Both suggested by Chris Wilson.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> (v2)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-10 14:30:25 +02:00
Chris Wilson 02978ff57a drm/i915: Fix write-read race with multiple rings
Daniel noticed a problem where is we wrote to an object with ring A in
the middle of a very long running batch, then executed a quick batch on
ring B before a batch that reads from the same object, its obj->ring would
now point to ring B, but its last_write_seqno would be still relative to
ring A. This would allow for the user to read from the object before the
GPU had completed the write, as set_domain would only check that ring B
had passed the last_write_seqno.

To fix this simply (and inelegantly), we bump the last_write_seqno when
switching rings so that the last_write_seqno is always relative to the
current obj->ring.

This fixes igt/tests/gem_write_read_ring_switch.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@vger.kernel.org
[danvet: Add note about the newly created igt which exercises this
bug.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-10 10:41:55 +02:00
Guenter Roeck c11e5f35ab Partially revert "drm/i915: unconditionally use mt forcewake on hsw/ivb"
This patch partially reverts commit 36ec8f8774 for
IvyBridge CPUs.

The original commit results in repeated 'Timed out waiting for forcewake old
ack to clear' messages on a Supermicro C7H61 board (BIOS version 2.00 and 2.00b)
with i7-3770K CPU. It ultimately results in a hangup if the system is highly
loaded. Reverting the commit for IvyBridge CPUs fixes the issue.

Issue a warning if the CPU is IvyBridge and mt forcewake is disabled, since
this condition can result in secondary issues.

v2: Only revert patch for Ivybridge CPUs
    Issue info message if mt forcewake is disabled on Ivybridge

Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=60541
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66139
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-10 08:03:45 +02:00
Maarten Lankhorst 0108bc8081 drm/nouveau: do not allow negative sizes for now
The API allows up to 64-bits allocations, but size is handled as int
inside nouveau almost everywhere. Until this is fixed it's better to
prevent negative sizes.

The 256 kB before INT_MAX is paranoia, because of the large page
aligning below that could flip it above INT_MAX.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-10 10:48:07 +10:00
Maarten Lankhorst 9b234db378 drm/nouveau: add falcon interrupt handler
This prevents 100% cpu usage on fermi cards when the exit interrupt
from the secret scrubber is not acked.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-10 10:48:07 +10:00
Ben Skeggs 00fc6f6f73 drm/nouveau: use dedicated channel for async moves on GT/GF chipsets.
The moves themselves were generally async to graphics previously, with
the exception that if the "main" channel is used to synchronise a
page flip at the same time, it can end up blocked for a noticable amount
of time for large buffer moves.

Not really critical, and there's better ways of handling this, but they
are all rather invasive, so this is fine for now.

Based on a patch by Maarten Lankhorst addressing the same issue.

Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-07-10 10:48:01 +10:00
Maarten Lankhorst 06b237ef39 drm/nouveau: bump fence timeout to 15 seconds
calim didn't like 150 seconds timeout, so lower the timeout for him.
15 seconds should still be plenty.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-10 10:48:00 +10:00
Maarten Lankhorst 4f3855997c drm/nouveau: do not unpin in nouveau_gem_object_del
This should no longer be required, and is harmful for framebuffer pinning.
Also add a warning if unpin causes the pin count to drop below 0.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-10 10:47:49 +10:00
Ben Skeggs 8dda53fca2 drm/nv50/kms: fix pin refcnt leaks
Weren't critical previously, the buffers would go away anyway.  But with
recent changes to core drm/ttm lockdep will get pissed off now, so let's
fix it.

Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-07-10 10:47:42 +10:00
Maarten Lankhorst fdfb833265 drm/nouveau: fix some error-path leaks in fbcon handling code
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-10 10:47:28 +10:00
Ben Skeggs 060810d7ab drm/nouveau: fix locking issues in page flipping paths
b580c9e2b7 introduced additional problems
while trying to solve issues that became apparent while porting to the
new reservation stuff.

The major problem was that the the previously mentioned patch took the
client mutex earlier than previously, but the pinning of new_bo can
can potentially cause a buffer move, which would result in attempting to
acquire the same mutex again.

This commit attempts to fix that "fix".

Thanks to Maarten for the tips on keeping lockdep happy and cooking :)

Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Acked-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
2013-07-10 10:47:12 +10:00
Linus Torvalds 2e17c5a97e Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie:
 "Okay this is the big one, I was stalled on the fbdev pull req as I
  stupidly let fbdev guys merge a patch I required to fix a warning with
  some patches I had, they ended up merging the patch from the wrong
  place, but the warning should be fixed.  In future I'll just take the
  patch myself!

  Outside drm:

  There are some snd changes for the HDMI audio interactions on haswell,
  they've been acked for inclusion via my tree.  This relies on the
  wound/wait tree from Ingo which is already merged.

  Major changes:

  AMD finally released the dynamic power management code for all their
  GPUs from r600->present day, this is great, off by default for now but
  also a huge amount of code, in fact it is most of this pull request.

  Since it landed there has been a lot of community testing and Alex has
  sent a lot of fixes for any bugs found so far.  I suspect radeon might
  now be the biggest kernel driver ever :-P p.s.  radeon.dpm=1 to enable
  dynamic powermanagement for anyone.

  New drivers:

  Renesas r-car display unit.

  Other highlights:

   - core: GEM CMA prime support, use new w/w mutexs for TTM
     reservations, cursor hotspot, doc updates
   - dvo chips: chrontel 7010B support
   - i915: Haswell (fbc, ips, vecs, watermarks, audio powerwell),
     Valleyview (enabled by default, rc6), lots of pll reworking, 30bpp
     support (this time for sure)
   - nouveau: async buffer object deletion, context/register init
     updates, kernel vp2 engine support, GF117 support, GK110 accel
     support (with external nvidia ucode), context cleanups.
   - exynos: memory leak fixes, Add S3C64XX SoC series support, device
     tree updates, common clock framework support,
   - qxl: cursor hotspot support, multi-monitor support, suspend/resume
     support
   - mgag200: hw cursor support, g200 mode limiting
   - shmobile: prime support
   - tegra: fixes mostly

  I've been banging on this quite a lot due to the size of it, and it
  seems to okay on everything I've tested it on."

* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (811 commits)
  drm/radeon/dpm: implement vblank_too_short callback for si
  drm/radeon/dpm: implement vblank_too_short callback for cayman
  drm/radeon/dpm: implement vblank_too_short callback for btc
  drm/radeon/dpm: implement vblank_too_short callback for evergreen
  drm/radeon/dpm: implement vblank_too_short callback for 7xx
  drm/radeon/dpm: add checks against vblank time
  drm/radeon/dpm: add helper to calculate vblank time
  drm/radeon: remove stray line in old pm code
  drm/radeon/dpm: fix display_gap programming on rv7xx
  drm/nvc0/gr: fix gpc firmware regression
  drm/nouveau: fix minor thinko causing bo moves to not be async on kepler
  drm/radeon/dpm: implement force performance level for TN
  drm/radeon/dpm: implement force performance level for ON/LN
  drm/radeon/dpm: implement force performance level for SI
  drm/radeon/dpm: implement force performance level for cayman
  drm/radeon/dpm: implement force performance levels for 7xx/eg/btc
  drm/radeon/dpm: add infrastructure to force performance levels
  drm/radeon: fix surface setup on r1xx
  drm/radeon: add support for 3d perf states on older asics
  drm/radeon: set default clocks for SI when DPM is disabled
  ...
2013-07-09 16:04:31 -07:00
Linus Torvalds 5f097cd249 Various fbdev changes for 3.11
* xilinxfb updates
  * Small cleanups and fixes to multiple drivers
  * OMAP display subsystem bug updates
  * imxfb dt support
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Merge tag 'fbdev-for-3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/plagnioj/linux-fbdev

Pull fbdev update from Jean-Christophe PLAGNIOL-VILLARD:
 "Various fbdev changes for 3.11
   - xilinxfb updates
   - Small cleanups and fixes to multiple drivers
   - OMAP display subsystem bug updates
   - imxfb dt support"

* tag 'fbdev-for-3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/plagnioj/linux-fbdev: (95 commits)
  video: imxfb: Add DT support
  video: i740fb: Make i740fb_init static
  fb: make fp_get_options name argument const
  video: mmp: fix graphics/video layer enable/mask swap issue
  video: mmp: fix memcpy wrong size for mmp_addr issue
  radeon: use pdev->pm_cap instead of pci_find_capability(..,PCI_CAP_ID_PM)
  aty128fb: use pdev->pm_cap instead of pci_find_capability(..,PCI_CAP_ID_PM)
  video: of_display_timing.h: Declare 'display_timing'
  fbdev: bfin-lq035q1-fb: Use dev_pm_ops
  fbmem: return -EFAULT on copy_to_user() failure
  OMAPDSS: DPI: Fix wrong pixel clock limit
  video: replace strict_strtoul() with kstrtoul()
  uvesafb: Correct/simplify warning message
  fb: fix atyfb unused data warnings
  fb: fix atyfb build warning
  video: imxfb: Make local symbols static
  video: udlfb: Make local symbol static
  video: udlfb: Use NULL instead of 0
  video: smscufx: Use NULL instead of 0
  video: remove unnecessary platform_set_drvdata()
  ...
2013-07-09 15:51:32 -07:00
Ville Syrjälä 885b012008 drm/i915: Fix VLV DP RBR/HDMI/DAC PLL LPF coefficients
I just got confirmation that we're using some old values for the PLL
LPF coefficients for DP RBR/HDMI/DAC on VLV. The
VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_9 document lists both values
by mistake, and apparently we had picked the wrong one. Change the
coefficients to the recommended values.

Changing the value doesn't appear to destabilize the VGA output picture
even with my sensitive HP ZR24w display. Also HDMI output to my TV still
works fine.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-09 22:27:33 +02:00
Daniel Vetter 897f9ed00a drm/i915: WARN if the bios reserved range is bigger than stolen size
v2: Bail out if we hit the WARN_ON to avoid fallout later on. Spotted
by Chris Wilson.

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-09 16:53:24 +02:00
Daniel Vetter 36c0cc616e drm/i915: clean up media reset on gm45
Originally I've thought that this fixes up the reset issues on my
gm45, but that was just a red herring due to b0rked testing.

Still I much prefer writing the right values (all other fields are
reserved) instead of potentially dragging gunk around. Hence also
clear the register to 0 after a reset.

Note that Cspec is a bit confused and doesn't explicitly say that all
the other bits in this register are "reserved, mbz" like usually.
Instead they're marked as "r/o, default value = 0" which semantically
amounts to the same thing.

v2: Stop claiming this fixes anything and return 0 if successful
instead of stack garbage.

v3: Pimp the commit message to explain exactly why I think the docs
allow us to ditch the rmw cycle, spurred by a discussion with Chris.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-09 16:52:19 +02:00
Imre Deak d4eead50eb drm/i915: fix lane bandwidth capping for DP 1.2 sinks
DP 1.2 compatible displays may report a 5.4Gbps maximum bandwidth which
the driver will treat as an invalid value and use 1.62Gbps instead. Fix
this by capping to 2.7Gbps for sinks reporting a 5.4Gbps max bw.

Also add a warning for reserved values.

v2:
- allow only bw values explicitly listed in the DP standard (Daniel,
  Chris)

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-09 16:35:50 +02:00
Daniel Vetter aaf8a51672 drm/i915: fix up ring cleanup for the i830/i845 CS tlb w/a
It's not a good idea to also run the pipe_control cleanup.

This regression has been introduced whith the original cs tlb w/a in

commit b45305fce5
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Mon Dec 17 16:21:27 2012 +0100

    drm/i915: Implement workaround for broken CS tlb on i830/845

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=64610
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: stable@vger.kernel.org
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-09 16:31:49 +02:00
Xiong Zhang 067556084a drm/i915: Correct obj->mm_list link to dev_priv->dev_priv->mm.inactive_list
obj->mm_list link to dev_priv->mm.inactive_list/active_list
obj->global_list link to dev_priv->mm.unbound_list/bound_list

This regression has been introduced in

commit 93927ca52a
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu Jan 10 18:03:00 2013 +0100

    drm/i915: Revert shrinker changes from "Track unbound pages"

Cc: stable@vger.kernel.org
Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
[danvet: Add regression notice.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-09 16:31:48 +02:00
Paulo Zanoni bf51d5e2cd drm/i915: switch disable_power_well default value to 1
Now that the audio driver is using our power well API, everything
should be working correctly, so let's give it a try.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-09 16:31:48 +02:00
Chris Wilson eaba1b8f33 drm/i915: Verify that our stolen memory doesn't conflict
Sanity check that the memory region found through the Graphics Base
of Stolen Memory is reserved and hidden from the rest of the system
through the use of the resource API.

v2: "Graphics Stolen Memory" is such a more bodacious name than the lame
    "i915 stolen", and convert to using devres for automagical cleanup of
    the resource. (danvet)

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
[danvet: Dump proper hexcodes.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-09 16:31:20 +02:00
Dave Airlie 774d8e34e4 Merge branch 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few more DPM fixes based on user testing.

* 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/dpm: implement vblank_too_short callback for si
  drm/radeon/dpm: implement vblank_too_short callback for cayman
  drm/radeon/dpm: implement vblank_too_short callback for btc
  drm/radeon/dpm: implement vblank_too_short callback for evergreen
  drm/radeon/dpm: implement vblank_too_short callback for 7xx
  drm/radeon/dpm: add checks against vblank time
  drm/radeon/dpm: add helper to calculate vblank time
  drm/radeon: remove stray line in old pm code
  drm/radeon/dpm: fix display_gap programming on rv7xx
  drm/radeon/dpm: implement force performance level for TN
  drm/radeon/dpm: implement force performance level for ON/LN
  drm/radeon/dpm: implement force performance level for SI
  drm/radeon/dpm: implement force performance level for cayman
  drm/radeon/dpm: implement force performance levels for 7xx/eg/btc
  drm/radeon/dpm: add infrastructure to force performance levels
  drm/radeon: fix surface setup on r1xx
  drm/radeon: add support for 3d perf states on older asics
  drm/radeon: set default clocks for SI when DPM is disabled
2013-07-09 10:49:39 +10:00
Dave Airlie fd0932d7f8 Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
Two minor fixes for regressions.

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6:
  drm/nvc0/gr: fix gpc firmware regression
  drm/nouveau: fix minor thinko causing bo moves to not be async on kepler
2013-07-09 10:48:41 +10:00
Alex Deucher f4dec31861 drm/radeon/dpm: implement vblank_too_short callback for si
Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:41:11 -04:00
Alex Deucher 76ad73e549 drm/radeon/dpm: implement vblank_too_short callback for cayman
Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:41:01 -04:00
Alex Deucher a84301c65d drm/radeon/dpm: implement vblank_too_short callback for btc
Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:52 -04:00
Alex Deucher d0b54bdc93 drm/radeon/dpm: implement vblank_too_short callback for evergreen
Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:42 -04:00
Alex Deucher b06195d994 drm/radeon/dpm: implement vblank_too_short callback for 7xx
Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:31 -04:00
Alex Deucher 4878306935 drm/radeon/dpm: add checks against vblank time
If the vblank time is too short to adjust mclk,
assume multiple displays (no mclk adjustments).

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:20 -04:00
Alex Deucher 66edc1c95d drm/radeon/dpm: add helper to calculate vblank time
Required for checking vblank time for mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:09 -04:00
Alex Deucher 7e1f3c0419 drm/radeon: remove stray line in old pm code
Looks like a remnant from an old rebase.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:40:00 -04:00
Alex Deucher 222dc9a072 drm/radeon/dpm: fix display_gap programming on rv7xx
Check the driver state rather than the register as the
crtc registers may not be enabled yet.

Should fix:
https://bugzilla.kernel.org/show_bug.cgi?id=60510
https://bugs.freedesktop.org/show_bug.cgi?id=66651

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-08 17:39:51 -04:00
Daniel Vetter 34b9674c78 drm/i915: convert debugfs creation/destruction to table
At least for the common cases where we only need special file
operations. The forcewake file is still rather more special.

v2: Fix up the debugfs unregister code.

v3: Actually squash in the right fixup.

Acked-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-08 22:04:46 +02:00
Daniel Vetter 5d536e2858 drm/i915: dvo needs a P2 divisor of 4
Section 1.5.4, "DPLL A Control Register" from Bspec about bit 23
"FPA0/A1 P2 Clock Divide":

0 = Divide by 2
1 = Divide by 4. This bit must be set in DVO non-gang mode

So copy the current limits (which should be good for i8xx) and create
a new set for dvo encoders.

Reviewed-by: Chris Wilson <chris@chris-wilson.oc.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-08 22:04:38 +02:00
Daniel Vetter 4a33e48d0e drm/i915: fix dvo DPLL regression
I've missed that intel_dvo_mode_set changes the dpll configuration.
Hence when I've reworked the sequence to only enable the dpll in the
crtc_enable callback in

commit 66e3d5c099
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Sun Jun 16 21:24:16 2013 +0200

    drm/i915: move i9xx dpll enabling into crtc enable function

that special DVO bit was lost. Some BSpec reading confirms that it's
only needed for DVO encoders. Section 1.5.4, "DPLL A Control Register"
for bit 30:

"2X Clock Enable. When driving In non-gang DVO modes such as a
connected flat panel or TV, a 2X" version of the clock is needed. When
not using the 2X output it should be disabled. This bit cannot be set
when driving the integrated LVDS port on devices such as Montara-GM."

Fix this regression up.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66516
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reported-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Partially-tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-08 22:04:37 +02:00
Ben Widawsky c6cfb32567 drm/i915: Embed drm_mm_node in i915 gem obj
Embedding the node in the obj is more natural in the transition to VMAs
which will also have embedded nodes. This change also helps transition
away from put_block to remove node.

Though it's quite an uncommon occurrence, it's somewhat convenient to not
fail at bind time because we cannot allocate the node. Though in
practice there are other allocations (like the request structure) which
would probably make this point not terribly useful.

Quoting Daniel:
Note that the only difference between put_block and remove_node is
that the former fills up the preallocation cache. Which we don't need
anyway and hence is just wasted space.

v2: Clean up the stolen preallocation code.
Rebased on the reserve_node patches
renames ggtt_ stuff to gtt_ stuff
WARN_ON if the object is already bound (which doesn't mean it's in the
bound list, tricky)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-08 22:04:36 +02:00
Ben Widawsky edd41a870f drm/i915: Kill obj->gtt_offset
With the getters in place from the previous patch this members serves no
purpose other than saving one spare pointer chase, which will be killed
in the next patch anyway.

Moving to VMAs, this members adds unnecessary confusion since an object
may exist at different offsets in different VMs.

v2: Properly preserve the stolen offset. This code is a bit hacky but it
all goes away when we embed the drm_mm_node and removes the need for the
incorrect patch I submitted previously: "Use gtt_space->start for stolen
reservation"

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-08 22:04:35 +02:00
Ben Widawsky f343c5f647 drm/i915: Getter/setter for object attributes
Soon we want to gut a lot of our existing assumptions how many address
spaces an object can live in, and in doing so, embed the drm_mm_node in
the object (and later the VMA).

It's possible in the future we'll want to add more getter/setter
methods, but for now this is enough to enable the VMAs.

v2: Reworked commit message (Ben)
Added comments to the main functions (Ben)
sed -i "s/i915_gem_obj_set_color/i915_gem_obj_ggtt_set_color/" drivers/gpu/drm/i915/*.[ch]
sed -i "s/i915_gem_obj_bound/i915_gem_obj_ggtt_bound/" drivers/gpu/drm/i915/*.[ch]
sed -i "s/i915_gem_obj_size/i915_gem_obj_ggtt_size/" drivers/gpu/drm/i915/*.[ch]
sed -i "s/i915_gem_obj_offset/i915_gem_obj_ggtt_offset/" drivers/gpu/drm/i915/*.[ch]
(Daniel)

v3: Rebased on new reserve_node patch
Changed DRM_DEBUG_KMS to actually work (will need fixing later)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-08 22:04:34 +02:00
Ben Widawsky 338710e7af drm: Change create block to reserve node
With the previous patch we no longer actually create a node, we simply
find the correct hole and occupy it. This very well could have been
squashed with the last patch, but since I already had David's review, I
figured it's easiest to keep it distinct.

Also update the users in i915. Conveniently this is the only user of the
interface.

CC: David Airlie <airlied@linux.ie>
CC: <dri-devel@lists.freedesktop.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: David Airlie <airlied@linux.ie>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-08 22:04:33 +02:00
Ben Widawsky b3a070cccb drm: pre allocate node for create_block
For an upcoming patch where we introduce the i915 VMA, it's ideal to
have the drm_mm_node as part of the VMA struct (ie. it's pre-allocated).
Part of the conversion to VMAs is to kill off obj->gtt_space. Doing this
will break a bunch of code, but amongst them are 2 callers of
drm_mm_create_block(), both related to stolen memory.

It also allows us to embed the drm_mm_node into the object currently
which provides a nice transition over to the new code.

v2: Reordered to do before ripping out obj->gtt_offset.
Some minor cleanups made available because of reordering.

v3: s/continue/break on failed stolen node allocation (David)
Set obj->gtt_space on failed node allocation (David)
Only unref stolen (fix double free) on failed create_stolen (David)
Free node, and NULL it in failed create_stolen (David)
Add back accidentally removed newline (David)

CC: <dri-devel@lists.freedesktop.org>
Reviewed-by: David Herrmann <dh.herrmann@gmail.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: David Airlie <airlied@linux.ie>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-08 22:04:32 +02:00
Ben Skeggs 06d5a24f08 Merge remote-tracking branch 'airlied/drm-next' into drm-nouveau-next 2013-07-08 13:40:34 +10:00
Maarten Lankhorst d2989b534e drm/nvc0/gr: fix gpc firmware regression
"drm/nve0-/gr: some new gpc registers can have multiple copies"
5ee86c4190 caused a regression for nvc0, because the bit indicating last
transfer has occured was no longer set, resulting in random system lockups.

Reported-by: Ronald Uitermark <ronald645@gmail.com>
Tested-by: Ronald Uitermark <ronald645@gmail.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-08 10:52:07 +10:00
Ben Skeggs 1bb3f6a252 drm/nouveau: fix minor thinko causing bo moves to not be async on kepler
Reported-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-08 10:52:02 +10:00
Alex Deucher 9b5de59629 drm/radeon/dpm: implement force performance level for TN
Allows you to force the selected performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:10:06 -04:00
Alex Deucher 5d5e559193 drm/radeon/dpm: implement force performance level for ON/LN
Allows you to force the selected performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:56 -04:00
Alex Deucher a160a6a336 drm/radeon/dpm: implement force performance level for SI
Allows you to force the selected performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:48 -04:00
Alex Deucher 170a47f010 drm/radeon/dpm: implement force performance level for cayman
Allows you to force a performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:38 -04:00
Alex Deucher 8b5e6b7f0e drm/radeon/dpm: implement force performance levels for 7xx/eg/btc
Allows you to limit the selected power levels via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:30 -04:00
Alex Deucher 70d01a5ee2 drm/radeon/dpm: add infrastructure to force performance levels
This allows you to force specific power levels within a power
state.  Due to hardware restrictions between generations, the
interface is limited to the following 3 selections:

auto: all levels enabled
low: forced to the lowest power level
high: forced to the highest power level

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:19 -04:00
Alex Deucher 67d5ced503 drm/radeon: fix surface setup on r1xx
r1xx asics have a slightly different surface register
setup compared to newer asics.  There is no specific
enable bit for macro tiling, rather, to disable macro
tiling, you need to set the surface pitch to 0.

With this fixed, the special rn50 handling can go.

Noticed-by: Mark Kettenis <mark.kettenis@xs4all.nl>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:11 -04:00
Alex Deucher edcaa5b125 drm/radeon: add support for 3d perf states on older asics
Certain older rv770 asics have both a performance and
a 3D performance state rather than just multiple performance
levels in the state power state.  The current code would
select the performance state rather than the 3D performance
state when the "performance" profile was selected.  This change
switches to the "balanced" profile by default which ends up being
the internal performance profile.  When the user selects the
"performance" profile, it selects the internal 3D performance
state so the user can select the higher performance modes.

For most asics this changes nothing.  For certain rv770 asics
with static performance and 3D performance states, this allows
you to select between then using by selecting the "balanced"
and "performance" dpm profiles.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:09:02 -04:00
Alex Deucher c6cf7777a3 drm/radeon: set default clocks for SI when DPM is disabled
Fix patching of vddc values for SI and enable manually forcing
clocks to default levels as per NI.

This improves the out of the box performance with SI asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-05 18:08:54 -04:00
Daniel Vetter b79480ba50 drm/i915: assert_spin_locked for pipestat interrupt enable/disable
Just to keep the paranoia equal also sprinkle locking asserts over the
pipestat interrupt enable/disable functions.

Again this results in false positives in the interrupt setup. Add
bogo-locking for these and a big comment explaining why it's there and
that it's indeed unnecessary.

v2: Fix up the spelling fail Paulo spotted in comments.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-05 23:56:24 +02:00
Daniel Vetter 190d6cd5cd drm/i915: less magic for stolen preallocated objects w/o gtt offset
A magic -1 is a obscure, especially since it's actually passed as an
unsigned, so depends upon the magic sign extension rules in C. This has
been added in

commit 3727d55e4d
Author: Jesse Barnes <jbarnes@virtuousgeek.org>
Date:   Wed May 8 10:45:14 2013 -0700

    drm/i915: allow stolen, pre-allocated objects to avoid GTT allocation v2

Use a proper #define instead. Spotted while reviewing Ben's
drm_mm_create_block changes.

v2: Cast the constant to u32 since otherwise we again have a type
mismatch. Suggested by Chris Wilson.

Cc: Ben Widawsky <ben@bwidawsk.net>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-05 23:56:18 +02:00
Daniel Vetter d94ab06827 drm/i915: Explicitly cast pipe -> intel_dpll_id
We only do this on IBX where there's a fixed pch dpll to pipe
assignment. Being explicit about it can't really hurt and makes
sparse happy.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-05 23:47:09 +02:00
Daniel Vetter e143a21c4d drm/i915: explicitly cast pipe -> cpu_transcoder
This makes sparse happy and also makes it a bit more obvious where we
pull off this trick - after all we're only allowed to do it eithe as a
default or on platforms where there is no disdinction between the pipe
and the cpu transcoder.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-05 23:47:08 +02:00
Dave Airlie 30f83b3716 Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
- GF117 acceleration support
- GK110 acceleration-with-blob-ucode support, and initial work towards
fixing our own ucode to be suitable.
- Large cleanups of fermi/kepler context handling

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (22 commits)
  drm/nva3/disp: Fix HDMI audio regression
  drm/nv50-/disp: Use output specific mask in interrupt
  drm/nouveau: use vmalloc for pgt allocation
  drm/nvc0-/gr: remove some more of the hardcoded register writes
  drm/nvc0-/gr: factor out yet more unknown magic into versioned functions
  drm/nvd7/devinit: use fermi class, not tesla
  drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16
  drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucode
  drm/nvf0/gr: build cs ucode for GK110
  drm/nvc0-/gr: extend one of the magic calculations for >4 GPCs
  drm/nvf0/gr: fix ddx shaders locking up on me
  drm/nvc0/devinit: minor typo
  drm/nvf0/gr: enable support, if external cs ucode is available
  drm/nvf0/gr: magic sequence that makes PGRAPH come out of hiding
  drm/nvf0/ce: enable support
  drm/nvf0/fifo: enable support
  drm/nvd7/gr: initial support
  drm/nvc0-/gr: generate cs register lists from grctx data
  drm/nvc0-/gr: tpc regs a subset of gpc, add separate list for gpc/unk regs
  drm/nve0-/gr: some new gpc registers can have multiple copies
  ...
2013-07-05 15:55:12 +10:00
Joonyoung Shim 6d35dea107 drm/cma: remove GEM CMA specific dma_buf functionality
We can use prime helpers instead.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 15:44:54 +10:00
Joonyoung Shim 78467dc5f7 drm/cma: add low-level hook functions to use prime helpers
Instead of using the dma_buf functionality for GEM CMA, we can use prime
helpers if we can provide low-level hook functions for GEM CMA.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 15:44:49 +10:00
Joonyoung Shim 7c397cd97b drm: add mmap function to prime helpers
This adds to call low-level mmap() from prime helpers.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 15:44:44 +10:00
Joonyoung Shim f9d8a1294d drm/prime: fix sgt NULL checking
The drm_gem_map_detach() can be called with sgt is NULL.

Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 15:36:20 +10:00
Dave Airlie 63eef6002b Merge branch 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos into drm-next
This is final pull request for 3.11. This resolves some memory leak
   issues, and includes some code and dt document file cleanups; just
   removed unnecessary descriptions.

   And the patch work for enhancing hdmiphy driver isn't in progress so
   this patch may go to 3.12.

* 'exynos-drm-next' of git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos:
  drm/exynos: remove duplicated error routine and unnecessary assign
  drm/exynos: fix pages allocation size in lowlevel_buffer_allocate
  drm/exynos: use drm_calloc_large when allocates pointer array
  drm/exynos: add error check routine in exynos_drm_open
  drm/exynos: initialize the buf_num in vp_video_buffer
  drm/exynos: remove dead code in vidi_power_on
  drm/exynos: fix not to remain exynos_gem_obj as a leak
  of/documentation: Update hpd gpio property for exynos_hdmi
2013-07-05 15:35:38 +10:00
Laurent Pinchart 59e32642d2 drm/rcar-du: Fix buffer pitch alignment
The DU requires a 16 pixels pitch alignement. Make sure dumb buffers are
allocated with the correct pitch, and validate the pitch when creating
frame buffers.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 15:35:13 +10:00
Laurent Pinchart 3463ff67bc drm/rcar-du: Don't ignore rcar_du_crtc_create() return value
Handle error cases correctly.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 15:34:56 +10:00
Ilia Mirkin bf03d1b293 drm/nva3/disp: Fix HDMI audio regression
This is the nva3 counterpart to commit beba44b17 (drm/nv84/disp: Fix
HDMI audio regression). The regression happened as a result of
refactoring in commit 8e9e3d2de (drm/nv84/disp: move hdmi control into
core).

Reported-and-tested-by: Max Baldwin <archerseven@gmail.com>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Cc: stable@vger.kernel.org
2013-07-05 14:43:59 +10:00
Emil Velikov 378f2bcdf7 drm/nv50-/disp: Use output specific mask in interrupt
The commit

   commit 476e84e126
   Author: Ben Skeggs <bskeggs@redhat.com>
   Date:   Mon Feb 11 09:24:23 2013 +1000

       drm/nv50-/disp: initial supervisor support for off-chip encoders

changed the write mask in one of the interrupt functions for on-chip encoders,
causing a regression in certain VGA dual-head setups. This commit reintroduces
the mask thus resolving the regression

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66129
Reported-and-Tested-by: Yves-Alexis <corsac@debian.org>
Cc: stable@vger.kernel.org [3.9+]
CC: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 14:22:29 +10:00
Marcin Slusarz d005f51eb9 drm/nouveau: use vmalloc for pgt allocation
Page tables on nv50 take 48kB, which can be hard to allocate in one piece.
Let's use vmalloc.

Signed-off-by: Marcin Slusarz <marcin.slusarz@gmail.com>
Cc: stable@vger.kernel.org [3.7+]
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:48:41 +10:00
Ben Skeggs 5c5ae7157d drm/nvc0-/gr: remove some more of the hardcoded register writes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:45:04 +10:00
Ben Skeggs d196e16ebf drm/nvc0-/gr: factor out yet more unknown magic into versioned functions
NVC1/NVD9 are the only chipsets that should have anything different
happen on them after this.  We previously weren't doing these
register modifications, and NVIDIA do.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:44:52 +10:00
Ben Skeggs 0bfd6f734a drm/nvd7/devinit: use fermi class, not tesla
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:44:43 +10:00
Ben Skeggs 60a4acd7c9 drm/nvf0-/gr: ctxsw scratch reg count got bumped to 16
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:44:35 +10:00
Ben Skeggs f8adeb82a9 drm/nvc0-/gr: remove hardcoding of UNK count/mask in GPCCS ucode
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:44:25 +10:00
Ben Skeggs 8f6fe26745 drm/nvf0/gr: build cs ucode for GK110
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:44:16 +10:00
Ben Skeggs 960b4381c5 drm/nvc0-/gr: extend one of the magic calculations for >4 GPCs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:44:09 +10:00
Ben Skeggs 0085a60524 drm/nvf0/gr: fix ddx shaders locking up on me
This can be generalised and used on GK104 (probably even GF117), but lets
just make it work for now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:44:03 +10:00
Ben Skeggs 18ac424651 drm/nvc0/devinit: minor typo
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:43:55 +10:00
Ben Skeggs 9d1c4c51ce drm/nvf0/gr: enable support, if external cs ucode is available
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:43:49 +10:00
Ben Skeggs b054aadfb0 drm/nvf0/gr: magic sequence that makes PGRAPH come out of hiding
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:43:40 +10:00
Ben Skeggs 9ec2dbba9f drm/nvf0/ce: enable support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:43:33 +10:00
Ben Skeggs 56fbd2b654 drm/nvf0/fifo: enable support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:43:25 +10:00
Maarten Lankhorst 26410c6798 drm/nvd7/gr: initial support
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:43:16 +10:00
Ben Skeggs a32b2ffb82 drm/nvc0-/gr: generate cs register lists from grctx data
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:43:11 +10:00
Ben Skeggs 70f824ac8c drm/nvc0-/gr: tpc regs a subset of gpc, add separate list for gpc/unk regs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:43:06 +10:00
Ben Skeggs 5ee86c4190 drm/nve0-/gr: some new gpc registers can have multiple copies
GK110 exposes more than one, and needs to be dealt with in the ctxsw
ucode just like the TPC sets are.

Broadcast is at +0xe00.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:42:57 +10:00
Ben Skeggs c03ff9e8fa drm/nvc0-/gr: pull out a group of separately context-switched gpc regs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:42:51 +10:00
Ben Skeggs 30f4e0870d drm/nvc0-/gr: make register lists from initvals functions
Generated context verified to be the same for all supported chipsets.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-05 13:42:32 +10:00
Dave Airlie 5ff91e4426 qxl: use drm helper hotplug support
This uses the helper to deal with hotplug so fbdev gets included.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 10:44:19 +10:00
Dave Airlie d84300bf79 qxl: add suspend/resume/hibernate support.
This adds suspend/resume and hibernate support for the KMS driver. it evicts
all the objects, turns off the outputs, and waits for the hw to go idle,

On resume, it resets the memslots, rings, monitors object and forces modeset.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 10:44:18 +10:00
Dave Airlie b86487a6b6 qxl: add fb and ttm entry points for use by suspend/resume.
This just ports some APIs like radeon uses to provide hooks for s/r to
call.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 10:44:18 +10:00
Dave Airlie 1e209117db qxl: add ring prep code for s/r
This prepare the ring code for s/r additions, the release ring will need
reinitialising.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 10:44:17 +10:00
Dave Airlie c9fdda2a2b qxl: prepare memslot code for suspend/resume
this splits out initing the hw memslots from the guest info, and
creates an entrypoint for s/r to use.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 10:44:17 +10:00
Dave Airlie 2bd6ce84e1 qxl: split monitors_config object creation out.
This splits the creation of the monitors config object out so we can
re-use it across suspend/resume later.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 10:44:16 +10:00
Dave Airlie c927215543 drm/qxl: set time on drawables from userspace
This just sets the qxl time on the drawables.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 10:44:16 +10:00
Dave Airlie 07f8d9bdb2 drm/qxl: add support for > 1 output
This adds support for a default of 4 heads, with a command line
parameter to change the default number.

It also overhauls the modesetting code to handle this case properly,
and send the correct things to the hardware at the right time.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 10:44:10 +10:00
Dave Airlie 5b8788c174 drm/qxl: make dynamic resizing work properly.
qxl has a feature to allow the userspace driver do arbitrary resizes
when the viewer resizes, this fixes it by removing unnecessary code
from the kernel side.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-05 10:43:19 +10:00
Linus Torvalds 80cc38b163 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
Pull trivial tree updates from Jiri Kosina:
 "The usual stuff from trivial tree"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (34 commits)
  treewide: relase -> release
  Documentation/cgroups/memory.txt: fix stat file documentation
  sysctl/net.txt: delete reference to obsolete 2.4.x kernel
  spinlock_api_smp.h: fix preprocessor comments
  treewide: Fix typo in printk
  doc: device tree: clarify stuff in usage-model.txt.
  open firmware: "/aliasas" -> "/aliases"
  md: bcache: Fixed a typo with the word 'arithmetic'
  irq/generic-chip: fix a few kernel-doc entries
  frv: Convert use of typedef ctl_table to struct ctl_table
  sgi: xpc: Convert use of typedef ctl_table to struct ctl_table
  doc: clk: Fix incorrect wording
  Documentation/arm/IXP4xx fix a typo
  Documentation/networking/ieee802154 fix a typo
  Documentation/DocBook/media/v4l fix a typo
  Documentation/video4linux/si476x.txt fix a typo
  Documentation/virtual/kvm/api.txt fix a typo
  Documentation/early-userspace/README fix a typo
  Documentation/video4linux/soc-camera.txt fix a typo
  lguest: fix CONFIG_PAE -> CONFIG_x86_PAE in comment
  ...
2013-07-04 11:40:58 -07:00
Daniel Vetter 035dc1e0f9 drm/i915: reinit status page registers after gpu reset
This fixes gpu reset on my gm45 - without this patch the bsd thing is
forever stuck since the seqno updates never reach the status page.

Tbh I have no idea how this ever worked without rewriting the hws
registers after a gpu reset.

To satisfy my OCD also give the functions a bit more consistent names:
- Use status_page everywhere, also for the physical addressed one.
- Use init for the allocation part and setup for the register setup
  part consistently.

Long term I'd really like to share the hw init parts completely
between gpu reset, resume and driver load, i.e. to call
i915_gem_init_hw instead of the individual pieces we might need.

v2: Add the missing paragraph to the commit message about what bug
exactly this patch here fixes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65495
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: lu hua <huax.lu@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-04 11:36:36 +02:00
Seung-Woo Kim 4bb615c5fb drm/exynos: remove duplicated error routine and unnecessary assign
There were duplicated error handling routines during allocating
pages in lowlevel_buffer_allocate() and g2d_userptr_get_dma_addr().
Also unnecessary NULL assignments for variable used not any more
are removed from g2d_userptr_get_dma_addr() and
g2d_userptr_put_dma_addr().

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-07-04 15:55:37 +09:00
YoungJun Cho 42ac99a720 drm/exynos: fix pages allocation size in lowlevel_buffer_allocate
When IOMMU is not supported, buf->pages has to be allocated to
assign the result of phys_to_page() which return type is struct
page *. So it is sufficient to allocate buf->pages with the size
of multiple struct page pointers.

Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-07-04 15:55:37 +09:00
YoungJun Cho af51a5e706 drm/exynos: use drm_calloc_large when allocates pointer array
If the type of object is pointer array, the drm_calloc_large() is
more suitable than kzalloc() for its allocation function. And uses
drm_free_large() instead of kfree() also.

Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-07-04 15:55:36 +09:00
YoungJun Cho ba3706c0f1 drm/exynos: add error check routine in exynos_drm_open
When the exynos_drm_subdrv_open() returns error, the file_priv
should be released and file->driver_priv set to NULL.

Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-07-04 15:55:36 +09:00
YoungJun Cho 782953ece3 drm/exynos: initialize the buf_num in vp_video_buffer
The buf_num in vp_video_buffer() should be 1 or 2, but it is not
initialized, and only set to 2 in NV12M or NV12MT cases.
So this patch initializes the buf_num with 1 as default.

Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-07-04 15:55:36 +09:00
YoungJun Cho cbb28bb09d drm/exynos: remove dead code in vidi_power_on
The type of input parameter enable is bool, so it does not need
to check whether true or false.

Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-07-04 15:55:36 +09:00
YoungJun Cho c58c1599cd drm/exynos: fix not to remain exynos_gem_obj as a leak
The exynos_drm_gem_create() only calls drm_gem_object_release()
when exynos_drm_alloc_buf() is failed, and exynos_gem_obj remains
as a leak, which is allocated in exynos_drm_gem_init().
So this patch fixes it not to remain as a leak.

Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
2013-07-04 15:55:36 +09:00
Seung-Woo Kim 04274cd058 drm: fix print format of sequence in trace point
seq of a trace point is unsigned int but print format was %d. So
it fixes the format as %u.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-04 10:55:27 +10:00
Seung-Woo Kim df9b6a9c33 drm: fix error routines in drm_open_helper
There are missing parts to handle error in drm_open_helper().
The priv->minor, assigned by idr_find() which can return NULL,
should be checked whether it is NULL or not before referencing it.
put_pid(), drm_gem_release(), and drm_prime_destory_file_private()
should be called when error happens after their pair functions are
called. If an error occurs after executing dev->driver->open()
which allocates driver specific per-file private data, then the
private data should be released.

Signed-off-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Chris Wilson <chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-04 10:53:37 +10:00
Seung-Woo Kim fe2ef78066 drm: add assertion for checking null edid to drm_edid_block_valid
If raw_edid of drm_edid_block_vaild() is null, it will crash, so
checking in bad label is removed and instead assertion is added at
the top of the function.
The type of return for the function is bool, so it fixes to return
true and false instead of 1 and 0.

Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-04 10:52:50 +10:00
Shuah Khan cf4b91f2d9 drm: Convert drm class driver from legacy pm ops to dev_pm_ops
Convert drivers/gpu/drm class to use dev_pm_ops for power management and
remove Legacy PM ops hooks. With this change, drm class registers
suspend/resume callbacks via class->pm (dev_pm_ops) instead of Legacy
class->suspend/resume. When __device_suspend() runs call-backs, it will
find class->pm ops for the drm class.

drm_class_suspend() hook calls driver legacy ops with the state information.
e.g: drm_class_suspend() calls into driver suspend routines
via drm_dev->driver->suspend(drm_dev, state).

Once drm_class_suspend() is converted to dev_pm_ops, it will no longer
have access to pm_transition which it has to pass into driver legacy
suspend calls. A new freeze and suspend hooks are added to address the not
having access to the state information. The new freeze and suspend hooks
simply call __drm_class_suspend() with the appropriate pm state information.
__drm_class_suspend() is the original suspend hook with a new name.

Signed-off-by: Shuah Khan <shuah.kh@samsung.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-04 10:50:26 +10:00
Dave Airlie d0aaa2836a Merge tag 'drm-intel-fixes-2013-07-03' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
Pile of fixes for 3.11. A bit large in patch count, but that's simply due
to two fixes being split up into really small parts. Also I've included a
few more vlv patches than I'd have included for other platforms. But since
vlv is officially supported for the first time only in 3.11 that shouldn't
result in unbearable risks.

Highlights:
- ghost eDP fixes for hsw from Paulo
- fix PCH detection in virtualized enviroments (Rui Guo)
- duct-tape dma sg construction when swiotlb is in use (Konrad), dupe with
  a patch in your drm-fixes branch
- fix sdvo hotplug on i965g
- tune down a bunch of dmesg ERRORs which can be hit under normal
  conditions
- detect invalid pitches for tiled scanout buffers (Chris)
- a pile of vlv fixes from Ville: rps improvements, fixes for the dpll
  LPF, fixup the sprite mmio offsets
- fix context size on hsw (Ben)
- locking fixes for the hotplug code, specifically the storm handling
- fix get_config on CPT (Xiong Zhang)
- Fix the domain tracking when an unlocked seqno wait was interrupt
  (Chris), this seems to explain tons of little corruption bugs in the
  ddx. Chris also added a nice igt to exercise this.
- work around stack-corrupting vnsprintf in our error state dumper

* tag 'drm-intel-fixes-2013-07-03' of git://people.freedesktop.org/~danvet/drm-intel: (39 commits)
  drm/i915: Don't try to tear down the stolen drm_mm if it's not there
  drm/i915: Break up the large vsnprintf() in print_error_buffers()
  drm/i915: Refactor the wait_rendering completion into a common routine
  drm/i915: Only clear write-domains after a successful wait-seqno
  drm/i915: correct intel_dp_get_config() function for DevCPT
  drm/i915: fix hpd interrupt register locking
  drm/i915: fold the no-irq check into intel_hpd_irq_handler
  drm/i915: fold the queue_work into intel_hpd_irq_handler
  drm/i915: fold the hpd_irq_setup call into intel_hpd_irq_handler
  drm/i915: s/hotplug_irq_storm_detect/intel_hpd_irq_handler/
  drm/i915: close tiny race in the ilk pcu even interrupt setup
  drm/i915: fix locking around ironlake_enable|disable_display_irq
  drm/i915: Fix context sizes on HSW
  drm/i915: Fix VLV sprite register offsets
  Revert "drm/i915: Don't use the HDMI port color range bit on Valleyview"
  drm/i915: s/LFP/LPF in DPIO PLL register names
  drm/i915: Fix VLV PLL LPF coefficients for DAC
  drm/i915: Jump to at least RPe on VLV when increasing the GPU frequency
  drm/i915: Don't increase the GPU frequency from the delayed VLV rps timer
  drm/i915: GEN6_RP_INTERRUPT_LIMITS doesn't seem to exist on VLV
  ...
2013-07-04 10:46:17 +10:00
Dave Airlie 1586ba727f Merge branch 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few more DPM fixes.

* 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux:
  drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag
  drm/radeon/tn: disable PG when changing UVD clocks
  drm/radeon/sumo: disable PG when changing UVD clocks
  drm/radeon/aruba: disable additional rlc features
  drm/radeon: fix endian bug in radeon_atom_get_mclk_range_table()
  drm/radeon/dpm: fix compilation with certain versions of gcc
  drm/radeon/dpm: clarify debugfs warning
2013-07-04 10:44:06 +10:00
Daniel Vetter e5ad449be6 drm/mm: WARN for unclean mm takedown
The usual drm driver has tons of different drm_mm memory managers so the drm
error message in dmesg is pretty useless. WARN instead so that we have the full
backtrace.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-04 10:01:12 +10:00
Daniel Vetter 2c54b13357 drm/mm: fix debug table BUG
In

commit 3a359f0b21
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Sat Apr 20 12:08:11 2013 +0200

    drm/mm: fix dump table BUG

I've failed to fix both instances of the regression introduced in

commit 9e8944ab56
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Thu Nov 15 11:32:17 2012 +0000

   drm: Introduce an iterator over holes in the drm_mm range manager

Patch this up in the same way by extracting the hole debug logic
into it's own function, since that'll also clarify the logic a bit.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-04 10:01:00 +10:00
Daniel Vetter 4a88f73f14 drm/prime: fix up handle_to_fd ioctl return value
In

commit da34242e5e
Author: YoungJun Cho <yj44.cho@samsung.com>
Date:   Wed Jun 26 10:21:42 2013 +0900

    drm/prime: add return check for dma_buf_fd

the failure case handling was fixed up. But in the case when we
already had the buffer exported it changed the return value:
Previously we've return 0 on success, now we return the fd.

This ABI change has been caught by i-g-t/prime_self_import/with_one_bo.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66436
Cc: YoungJun Cho <yj44.cho@samsung.com>
Cc: Seung-Woo Kim <sw0312.kim@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Tested-by: lu hua <huax.lu@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reviewed-by: YoungJun Cho <yj44.cho@samsung.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-04 09:58:55 +10:00
Dave Jones a95681058e radeon: remove redundant __list_for_each definition from mkregtable.c
Signed-off-by: Dave Jones <davej@redhat.com>
Cc: Dave Airlie <airlied@linux.ie>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-07-03 16:07:43 -07:00
Jani Nikula dcf6d29483 drm/i915: quirk away phantom LVDS on Intel's D525MW mainboard
This replaceable mainboard only has a VGA-out, yet it claims to also have
a connected LVDS header.

Addresses https://bugs.freedesktop.org/show_bug.cgi?id=65256

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reported-by: Cornel Panceac <cpanceac@gmail.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: <annndddrr@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-07-03 16:07:42 -07:00
Chris Wilson e5614f0c2d drm/i915: quirk away phantom LVDS on Intel's D510MO mainboard
This replaceable mainboard only has a VGA-out, yet it claims to also have
a connected LVDS header.

Addresses https://bugs.freedesktop.org/show_bug.cgi?id=63860

[jani.nikula@intel.com: use DMI_EXACT_MATCH for board name.]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reported-by: <annndddrr@gmail.com>
Cc: Cornel Panceac <cpanceac@gmail.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Greg KH <greg@kroah.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2013-07-03 16:07:42 -07:00
Alex Deucher 338a95a955 drm/radeon/sumo: implement support for disable_gfx_power_gating_in_uvd flag
Some asic revisions need to disable PG when UVD is active.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:31 -04:00
Alex Deucher 62fa44bf7b drm/radeon/tn: disable PG when changing UVD clocks
Causes hangs for some people.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:30 -04:00
Alex Deucher 2b90eddcd7 drm/radeon/sumo: disable PG when changing UVD clocks
Causes hangs for some people.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:30 -04:00
Alex Deucher 0124853eb1 drm/radeon/aruba: disable additional rlc features
They cause problems with dynamic clocking.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:29 -04:00
Alex Deucher e631227f69 drm/radeon: fix endian bug in radeon_atom_get_mclk_range_table()
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-03 17:37:28 -04:00
Mike Lothian bf0936e196 drm/radeon/dpm: fix compilation with certain versions of gcc
Add #include <linux/seq_file.h> to *_dpm.c files

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-02 18:32:01 -04:00
Linus Torvalds 63580e51bb Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs
Pull VFS patches (part 1) from Al Viro:
 "The major change in this pile is ->readdir() replacement with
  ->iterate(), dealing with ->f_pos races in ->readdir() instances for
  good.

  There's a lot more, but I'd prefer to split the pull request into
  several stages and this is the first obvious cutoff point."

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: (67 commits)
  [readdir] constify ->actor
  [readdir] ->readdir() is gone
  [readdir] convert ecryptfs
  [readdir] convert coda
  [readdir] convert ocfs2
  [readdir] convert fatfs
  [readdir] convert xfs
  [readdir] convert btrfs
  [readdir] convert hostfs
  [readdir] convert afs
  [readdir] convert ncpfs
  [readdir] convert hfsplus
  [readdir] convert hfs
  [readdir] convert befs
  [readdir] convert cifs
  [readdir] convert freevxfs
  [readdir] convert fuse
  [readdir] convert hpfs
  reiserfs: switch reiserfs_readdir_dentry to inode
  reiserfs: is_privroot_deh() needs only directory inode, actually
  ...
2013-07-02 09:28:37 -07:00
Ville Syrjälä e8474409d7 drm/i915: Use wait_for() to wait for Punit to change GPU freq on VLV
Use wait_for() instead of the open coded loop to avoid spreading the
same old timeout related bugs.

This changes the loop to use msleep(1) instead of udelay(10) when the
Punit had not yet completed the frequency change. In practice that
doesn't seem to hurt performance as the Punit appears to be ready pretty
much always.

Also give the status bit a name, instead of using the magic number 1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-02 15:40:23 +02:00
Alex Deucher 713759291c drm/radeon/dpm: clarify debugfs warning
For chips without debugfs dpm support say that it's not
implemented rather than not supported to avoid confusion
about DPM support in general.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-02 09:14:08 -04:00
Daniel Vetter 446f8d81ca drm/i915: Don't try to tear down the stolen drm_mm if it's not there
Every other place properly checks whether we've managed to set
up the stolen allocator at boot-up properly, with the exception
of the cleanup code. Which results in an ugly

*ERROR* Memory manager not clean. Delaying takedown

at module unload time since the drm_mm isn't initialized at all.

v2: While at it check whether the stolen drm_mm is initialized instead
of the more obscure stolen_base == 0 check.

v3: Fix up the logic. Also we need to keep the stolen_base check in
i915_gem_object_create_stolen_for_preallocated since that can be
called before stolen memory is fully set up. Spotted by Chris Wilson.

v4: Readd the conversion in i915_gem_object_create_stolen_for_preallocated,
the check is for the dev_priv->mm.gtt_space drm_mm, the stolen
allocatot must already be initialized when calling that function (if
we indeed have stolen memory).

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65953
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: lu hua <huax.lu@intel.com> (v3)
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-02 11:47:19 +02:00
Jesse Barnes 510d5f2f6b drm/i915: split encoder get_config calls from crtc get_clock calls
This should help on HSW, where we don't currently have a get_clock call.

Reported-by: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-02 09:44:29 +02:00
David Herrmann 77ef8bbc87 drm: make drm_mm_init() return void
There is no reason to return "int" as this function never fails.
Furthermore, several drivers (ast, sis) already depend on this.

Signed-off-by: David Herrmann <dh.herrmann@gmail.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2013-07-02 13:34:41 +10:00
Alex Deucher 7982128c3d drm/radeon/dpm: add debugfs support for SI
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:09:06 -04:00
Alex Deucher bdf0c4f07d drm/radeon/dpm: add debugfs support for cayman
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:57 -04:00
Alex Deucher 490ab9314b drm/radeon/dpm: add debugfs support for TN
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:49 -04:00
Alex Deucher fb70160c5f drm/radeon/dpm: add debugfs support for ON/LN
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:41 -04:00
Alex Deucher bd210d11cd drm/radeon/dpm: add debugfs support for 7xx/evergreen/btc
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:32 -04:00
Alex Deucher 242916a5ee drm/radeon/dpm: add debugfs support for rv6xx
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:24 -04:00
Alex Deucher 1316b79256 drm/radeon/dpm: add infrastructure to support debugfs info
This lays the frameworks to report realtime power level
feedback.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:08:15 -04:00
Alex Deucher 7ad8d0687b drm/radeon/dpm: re-enable state transitions for Cayman
Was disabled due to stability issues on certain boards
caused by the a bug in the parsing of the atom mc reg tables.
That's fixed now so re-enable.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:07:18 -04:00
Alex Deucher 4b5c006ef2 drm/radeon/dpm: re-enable state transitions for BTC
Was disabled due to stability issues on certain boards
caused by the a bug in the parsing of the atom mc reg tables.
That's fixed now so re-enable.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 16:04:02 -04:00
Alex Deucher 4da18e26e0 drm/radeon: fix typo in radeon_atom_init_mc_reg_table()
Bad pointer math.  Fixes hangs in state transitions with
BTC+ asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 15:46:49 -04:00
Alex Deucher 5c7524bf06 drm/radeon/atom: fix endian bug in radeon_atom_init_mc_reg_table()
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 15:46:40 -04:00
Alex Deucher aa71d830c4 drm/radeon: remove sumo dpm/uvd bringup leftovers
Function doesn't do anything useful.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2013-07-01 15:46:32 -04:00
Jesse Barnes 6f02488e3a drm/i915: fixup messages in pipe_config_compare
Print out the flag that failed and fix up a mismatched paren.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 19:39:56 +02:00
Mika Kuoppala ef86ddced7 drm/i915: add error_state sysfs entry
As getting error state doesn't anymore require big kmallocs,
make error state accessible also from sysfs.

v2: - error state clearing (Chris Wilson)
    - user hint, proper access mode bits and name (Daniel Vetter)

v3: release resources in proper order (Chris Wilson)

Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Apply Chris' s/error_state/error/ bikeshed on the sysfs
name. Also update the dmesg message, spotted by Chris.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 19:39:31 +02:00
Mika Kuoppala 4dc955f7f5 drm/i915: introduce i915_error_state_buf_init
Make function for struct i915_error_state_buf initialization
and export it, for sysfs and debugfs.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 19:38:20 +02:00
Mika Kuoppala 95d5bfb3ac drm/i915: export error state ref handling
In preparation for sysfs error state access,
export ref error state ref counting interface.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 19:38:19 +02:00
Mika Kuoppala fc16b48be6 drm/i915: export error state to string conversion
In preparation for accessing error state from sysfs, export
error state to string conversion function. Also tuck buffer
error handling inside the function.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 19:38:19 +02:00
Jesse Barnes 319d9827eb drm/i915: flip on a no fb -> fb transition if crtc is active v3
If the crtc is active, we can simply flip a new fb onto it, provided the
other mode setting reqs are met.  Otherwise, we'll need to do a full
mode set to re-enable the crtc.

v2: check for crtc active and set mode_changed accordingly
v3: add module parameter, i915.fastboot, to control no fb -> fb flip behavior

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 19:38:18 +02:00
Jesse Barnes 4d6a3e63bc drm/i915: turn off panel fitting at flip time if needed v2
Need better pfit tracking to do this right.

v2: use fastboot param around this hack

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 19:38:17 +02:00
Jesse Barnes babea61dfb drm/i915: copy fetched mode state into crtc at setup_hw time v5
We already fetch and track other state into the main CRTC and encoder
structs, and for fastboot we need to do the same with the mode and clock
data we read out.

v2: fix debug print
v3: use fastboot param around state copy
v4: set clock and flags for crtc here instead of in setup_hw_state
v5: rename function to intel_crtc_mode_from_pipe_config for consistency (Chris)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 19:38:17 +02:00
Jesse Barnes f1f644dc66 drm/i915: get mode clock when reading the pipe config v9
We need this for comparing modes between configuration changes.

The tricky part is to allow us to reuse the new get_clock stuff to
recover the lvds clock on gen2/3 when neither the vbt has an lvds mode
nor the panel a (useful) EDID.

v2: try harder to calulate non-simple pixel clocks (Daniel)
    call get_clock after getting the encoder config, needed for pixel multiply
    (Jesse)
v3: drop get_clock now that the pixel_multiply has been moved into
    get_pipe_config
v4: re-add get_clock; we need to get the pixel multiplier in the
    encoder, so need to calculate the clock value after the encoder's
    get_config is called
v5: drop hsw clock_get, still needs to be written
v6: add fuzzy clock check (Daniel)
v7: wrap fuzzy clock check under !IS_HASWELL
    use port_clock field rather than a new CPU eDP clock field in crtc_config
v8: remove stale pixel_multiplier sets (Daniel)
    multiply by pixel_multiplier in 9xx clock get too (Daniel)
v9: make sure we set pixel_multiplier before calling clock_get from mode_get
    for LVDS (Daniel)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Add some explanation to the commit message about why we have
to jump through a few hoops. Also remove the rebase-fail hunk from
intel_sdvo.c]
[danvet: Squash in the fixup from Jesse to also call ->get_clock in
the modeset state checker.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 19:37:53 +02:00
Jesse Barnes 2385bdf078 drm/i915: add fastboot param for fast & loose mode setting
Handling all the state properly for fastboot is still not yet done by
far, but we need some way to be able to test what we currently have.
So hide the not-yet-quite-complete stuff behind a module option.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Add a real commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:28:02 +02:00
Daniel Vetter c93f54cf7d drm/i915: pixel multiplier readout support for pch ports
Now that we painstakingly track the shared pch dplls we can finally
implement pixel mutliplier readout support for pch ports, too.

v2: Undo the temporary hack to disable the sdvo pixel multiplier
cross-checking.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:28:01 +02:00
Ben Widawsky 911bdf0ae6 drm/i915: Move gtt_mtrr to i915_gtt
for file in `ls drivers/gpu/drm/i915/*.c` ; do
	sed -i "s/mm.gtt_mtrr/gtt.mtrr/" $file;
done

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:28:01 +02:00
Ben Widawsky 5c3fe8b03e drm/i915: Move fbc members out of line
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
[danvet: Resolve conflict with Damien's FBC_CHIP_DEFAULT no fbc
reason.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:28:00 +02:00
Ben Widawsky b2f21b4dfd drm/i915: Use gtt shortform where possible
Just for compactness.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:59 +02:00
Ben Widawsky 80a74f7f9c drm/i915: Drop dev from pte_encode
The original pte_encode function needed the dev argument so we could do
platform specific handling via IS_GENX, etc. With the merging of a pte
encoding function there should never been a need to quirk away gen
specific details.

The patch doesn't do much but makes the upcoming reworks in gtt/ppgtt/mm
slightly (albeit, ever so) easier.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:59 +02:00
Ben Widawsky 6716724006 drm/i915: Combine scratch members into a struct
There isn't any special reason to do this other than it makes it obvious
that the two members are connected.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:58 +02:00
Ben Widawsky 84f1356058 drm/i915: Really share scratch page
A previous patch had set up the ppgtt and ggtt to use the same scratch
page, but still kept around both pointers. Kill it, it's not needed and
gets in our way for upcoming cleanups.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:57 +02:00
Ben Widawsky 6670a5a5c7 drm/i915: make PDE|PTE platform specific
Nothing outside of i915_gem_gtt.c and more specifically, the relevant
gen specific init function should need to know about number of PDEs, or
PTEs per PD. Exposing this will only lead to circumventing using the
upcoming VM abstraction.

To accomplish this, move the defines into the .c file, rename the PDE
define to be GEN6, and make the PTE count less of a magic number.

The remaining code in the global gtt setup is a bit messy, but an
upcoming patch will clean that one up.

v2: Don't hardcode number of PDEs (Daniel + Jesse)
Reworded commit message to reflect change.

Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:57 +02:00
Ben Widawsky 26b7c22465 drm/i915: Extract error buffer capture
This helps when we have per VM buffer capturing.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:56 +02:00
Ben Widawsky 5476f8505b drm/i915: Remove extra error state NULL
Not only was there an extra, but since we now kzalloc the error state,
we don't need either.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:56 +02:00
Ville Syrjälä 165e901caa drm/i915: Mask out hardware status bits from VLV DPLL register
The DPLL lock bit, and the DPIO phy status bits are read-only and
controlled by the hardware, so they will never be set by the driver.
Mask them out when reading the hw state, so that the state
comparison won't fail.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuosugeek.org>
[danvet: Jesse asked for a code comment and I wholeheartly agree, so
added one.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:55 +02:00
Daniel Vetter f6736a1a7b drm/i915: s/pre_pll/pre/ on the lvds port enable function
i9xx doesn't use pre_enable at all, so we can fold this in now.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:54 +02:00
Daniel Vetter 66e3d5c099 drm/i915: move i9xx dpll enabling into crtc enable function
Now that we have the proper pipe config to track this, we don't need
to write any registers any more.

Note that for platforms without DPLL_MD (pre-gen4) which store the
pixel mutliplier in the DPLL register I've decided to keep the
seemingly "redundant" write: The comment right below saying "do this
trice for luck" doesn't instill confidence ...

v2: Drop a few now unnecessary local variables and switch the enable
function to take a struct intel_crtc * to simply arguments.

v3: Rebase on top of the newly-colored BUG_ON.

v4: Amend commit message to alliviate Imre's comment about the
redudant DPLL write for the pixel mutliplier.

Cc: Imre Deak <imre.deak@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:54 +02:00
Daniel Vetter 8bcc2795a6 drm/i915: hw state readout for i9xx dplls
In addition to existing stuff we also need to track DPLL_MD on gen4
and vlv. This is prep work so that we can move the dpll enable
sequence out from the ->mode_set callback into the crtc enabling
functions.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:53 +02:00
Daniel Vetter 952735ee41 drm/i915: move encoder pre enable hooks togther on ilk+
The ->pre_enable hook is only used for the cpu edp port on ilk-ivb, so
we can safely move it up across the fdi pll enabling.

Unfortunately we can't (yet) merge in the pre_pll enable hook despite
that only lvds uses it on ilk-ivb: Since the same lvds hook is also
need on i9xx platforms we need to fix up the pll enabling sequence
there, too.

Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:52 +02:00
Daniel Vetter 55607e8aaa drm/i915: asserts for lvds pre_enable
Lots of bangin my head against the wall^UExperiments have shown that
we really need to enable the lvds port before we enable plls. Strangely
that seems to include the fdi rx pll on the pch.

Note that the pch pll assert can fire since the lvds port has it's own
special clock source settings in the DPLL register, which means it
will never have a shared dpll (since there's only one LVDS port).

Anyway, encode this new evidence with a few nice WARNs.

v2: Incorporate review comments from Imre.
- Explain why lvds can't have a shared dpll.
- Update the WARN output.

Cc: Imre Deak <imre.deak@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:51 +02:00
Daniel Vetter 87442f732b drm/i915: duplicate intel_enable_pll into i9xx and vlv versions
Mostly since I _really_ don't want to touch the vlv hell.

No code change, just duplication. Also kill a now seriously outdated
code comment - the remark about the dvo encoder is now handled with
the pipe A quirk.

v2: Update the BUG_ONs as suggested by Jani (both in vlv_ and i9xx_
functions, since the split happens here).

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:51 +02:00
Daniel Vetter b89a1d395b drm/i915: use sw tracked state to select shared dplls
Just yet another prep step to be able to do all this up-front, before
we've set up any of the shared dplls in the new state. This will
eventually be useful for atomic modesetting.

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:50 +02:00
Daniel Vetter 15bdd4cff4 drm/i915: consolidate pch pll enable sequence
It's been splattered over 3 different places all doing random things.
Now we have (mostly) the same sequence as i8xx/i9xx, but all called
from the crtc_enable hook (through the pll->enable function):
- write new dividers
- enable vco and wait for stable clocks
- write again for the pixel mutliplier

I've left the seemingly random 200 usec delay in there, just in case.

Also move the encoder->pre_pll_enable hook into the crtc_enable
function, at the same spot we currently have a hack to enable the lvds
port. Since that hack is now redundant, kill it.

While doing this patch I've learned the hard way that we can only fire
up the LVDS port if both the pch dpll _and_ the fdi rc pll are not yet
enabled. Otherwise things go haywire, at least on cpt.

v2: It is paramount to write the FPx divisors before we enable the
the vco by writing to the DPLL registers, for otherwise the divisors
won't get updated. This is in line with the i8xx/i9xx dpll.

v3: To keep the nice abstraction add a ->mode_set callback to set the
divisors. Also streamline the enabling/disabling code a bit by
removing some cargo-cult duplication and clearing registers where
possible in the ->disable hook.

v4: Remove now unused local variable.

Acked-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:49 +02:00
Damien Lespiau 3ef8fb5ae2 drm/i915: Bail out once we've found the context object
Once we've found the the context object programmed in CCID, there's no
need to look the other objects in the list.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:49 +02:00
Damien Lespiau f4db9321a7 drm/i915: Fix a couple of "should it be static?" sparse warnings
A genuine 'static' omission and 2 other warnings triggered by not
including the header where those functions where defined.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:48 +02:00
Damien Lespiau aee56cff33 drm/i915: Fix a few style issues found by checkpatch.pl
Missing spaces and misplaced '*'.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:47 +02:00
Damien Lespiau 267f0c90ac drm/i915: Use seq_puts/seq_putc when possible
Caught with checkpatch.pl.

Suggested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:47 +02:00
Damien Lespiau 8a5729a373 drm/i915: Fix reason for per-chip disabling of FBC
When running on my snb machine, recent kernels display successively:

[drm:intel_update_fbc], fbc set to per-chip default
[drm:intel_update_fbc], fbc disabled per module param

But no module param is set. This happens because the check for the
module parameter uses a variable that has been overridden inside the
"per-chip default" code.

Fix up the logic and add another reason for the FBC to the be disabled.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:46 +02:00
Damien Lespiau b63fb44c65 drm/i915: Make intel_enable_fbc() static
This function has no user outside of intel_pm.c.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:45 +02:00
Paulo Zanoni 6cdcb5e73f drm/i915: invert the verbosity of intel_enable_fbc
We currently print a DRM_DEBUG_KMS message on the happy path and don't
print anything on the "failed to allocate" path. On some desktop
environments (e.g., Unity) I see the "scheduling delayed FBC enable"
thousands and thousands of times on my dmesg.

So kill the useless message for the happy case, saving a lot of dmesg
space, and properly signal the "kzalloc fail" case.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Zoltan Nyul <zoltan.nyul@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:27:44 +02:00
Chris Wilson baf27f9b17 drm/i915: Break up the large vsnprintf() in print_error_buffers()
So it appears that I have encountered some bogosity when trying to call
i915_error_printf() with many arguments from print_error_buffers(). The
symptom is that the vsnprintf parser tries to interpret an integer arg
as a character string, the resulting OOPS indicating stack corruption.
Replacing the single call with its 13 format specifiers and arguments
with multiple calls to i915_error_printf() worked fine. This patch goes
one step further and introduced i915_error_puts() to pass the strings
simply.

It may not fix the root cause, but it does prevent my box from dying and
I think helps make print_error_buffers() more friendly.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66077
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:15:01 +02:00
Chris Wilson d26e3af842 drm/i915: Refactor the wait_rendering completion into a common routine
Harmonise the completion logic between the non-blocking and normal
wait_rendering paths, and move that logic into a common function.

In the process, we note that the last_write_seqno is by definition the
earlier of the two read/write seqnos and so all successful waits will
have passed the last_write_seqno. Therefore we can unconditionally clear
the write seqno and its domains in the completion logic.

v2: Add the missing ring parameter, because sometimes it is good to have
things compile.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:15:01 +02:00
Chris Wilson daa13e1ca5 drm/i915: Only clear write-domains after a successful wait-seqno
In the introduction of the non-blocking wait, I cut'n'pasted the wait
completion code from normal locked path. Unfortunately, this neglected
that the normal path returned early if the wait returned early. The
result is that read-only waits may return whilst the GPU is still
writing to the bo.

Fixes regression from
commit 3236f57a01 [v3.7]
Author: Chris Wilson <chris@chris-wilson.co.uk>
Date:   Fri Aug 24 09:35:09 2012 +0100

    drm/i915: Use a non-blocking wait for set-to-domain ioctl

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66163
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:15:00 +02:00
Xiong Zhang 63000ef656 drm/i915: correct intel_dp_get_config() function for DevCPT
On DevCPT, the control register for Transcoder DP Sync Polarity is
TRANS_DP_CTL, not DP_CTL.
Without this patch, Many call trace occur on CPT machine with DP monitor.
The call trace is like: *ERROR* mismatch in adjusted_mode.flags(expected X,found X)

v2: use intel-crtc to simple patch, suggested by Daniel.

Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com>
[danvet: Extend the encoder->get_config comment to specify that we now
also depend upon intel_encoder->base.crtc being correct. Also bikeshed
s/intel_crtc/crtc/.]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65287
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:59 +02:00
Daniel Vetter b5ea2d5681 drm/i915: fix hpd interrupt register locking
Our interrupt handler (in hardirq context) could race with the timer
(in softirq context), hence we need to hold the spinlock around the
call to ->hdp_irq_setup in intel_hpd_irq_handler, too.

But as an optimization (and more so to clarify things) we don't need
to do the irqsave/restore dance in the hardirq context.

Note also that on ilk+ the race isn't just against the hotplug
reenable timer, but also against the fifo underrun reporting. That one
also modifies the SDEIMR register (again protected by the same
dev_priv->irq_lock).

To lock things down again sprinkle a assert_spin_locked. But exclude
the functions touching SDEIMR for now, I want to extract them all into
a new helper function (like we do already for pipestate, display
interrupts and all the various gt interrupts).

v2: Add the missing 't' Egbert spotted in a comment.

v3: Actually fix the right misspelled comment (Paulo).

Cc: Egbert Eich <eich@suse.de>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:59 +02:00
Daniel Vetter 91d131d21e drm/i915: fold the no-irq check into intel_hpd_irq_handler
The usual pattern for our sub-function irq_handlers is that they check
for the no-irq case themselves. This results in more streamlined code
in the upper irq handlers.

v2: Rebase on top of the i965g/gm sdvo hpd fix.

Cc: Egbert Eich <eich@suse.de>
Reviewed-by: Egbert Eich <eich@suse.de>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:58 +02:00
Daniel Vetter 5876fa0d9e drm/i915: fold the queue_work into intel_hpd_irq_handler
Everywhere the same.

Note that this patch leaves unnecessary braces behind, but the next
patch will kill those all anyway (including the if itself) so I've
figured I can keep the diff a bit smaller.

v2: Rebase on top of the i965g/gm sdvo hpd fix.

Cc: Egbert Eich <eich@suse.de>
Reviewed-by: Egbert Eich <eich@suse.de>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:57 +02:00
Daniel Vetter 10a504de56 drm/i915: fold the hpd_irq_setup call into intel_hpd_irq_handler
We already have a vfunc for this (and other parts of the hpd storm
handling code already use it).

v2: Rebase on top of the i965g/gm sdvo hpd fix.

Cc: Egbert Eich <eich@suse.de>
Reviewed-by: Egbert Eich <eich@suse.de>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:57 +02:00
Daniel Vetter 22062dbacf drm/i915: s/hotplug_irq_storm_detect/intel_hpd_irq_handler/
The combination of Paulo's fifo underrun detection code and Egbert's
hpd storm handling code unfortunately made the hpd storm handling code
racy.

To avoid duplicating tricky interrupt locking code over all platforms
start with a bit of refactoring. This patch is the very first step
since in the end the irq storm handling code will handle all hotplug
logic (and so also encapsulate the locking nicely).

v2: Rebase on top of the i965g/gm sdvo hpd fix.

Cc: Egbert Eich <eich@suse.de>
Reviewed-by: Egbert Eich <eich@suse.de>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:56 +02:00
Daniel Vetter 6005ce4243 drm/i915: close tiny race in the ilk pcu even interrupt setup
By the time we write DEIER in the postinstall hook the interrupt
handler could run any time. And it does modify DEIER to handle
interrupts.

Hence the DEIER read-modify-write cycle for enabling the PCU event
source is racy. Close this races the same way we handle vblank
interrupts: Unconditionally enable the interrupt in the IER register,
but conditionally mask it in IMR. The later poses no such race since
the interrupt handler does not touch DEIMR.

Also update the comment, the clearing has already happened
unconditionally above.

v2: Actually shove the updated comment into the right train^W commit,
as spotted by Paulo.

Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:55 +02:00
Daniel Vetter 4bc9d43015 drm/i915: fix locking around ironlake_enable|disable_display_irq
The haswell unclaimed register handling code forgot to take the
spinlock. Since this is in the context of the non-rentrant interupt
handler and we only have one interrupt handler it is sufficient to
just grab the spinlock - we do not need to exclude any other
interrupts from running on the same cpu.

To prevent such gaffles in the future sprinkle assert_spin_locked over
these functions. Unfornately this requires us to hold the spinlock in
the ironlake postinstall hook where it is not strictly required:
Currently that is run in single-threaded context and with userspace
exlcuded from running concurrent ioctls. Add a comment explaining
this.

v2: ivb_can_enable_err_int also needs to be protected by the spinlock.
To ensure this won't happen in the future again also sprinkle a
spinlock assert in there.

v3: Kill the 2nd call to ivb_can_enable_err_int I've accidentally left
behind, spotted by Paulo.

Cc: Paulo Zanoni <przanoni@gmail.com>
Reviewed-by: Paulo Zanoni <przanoni@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:55 +02:00
Ben Widawsky a0de80a0e0 drm/i915: Fix context sizes on HSW
With updates to the spec, we can actually see the context layout, and
how many dwords are allocated. That table suggests we need 70720 bytes
per HW context. Rounded up, this is 18 pages. Looking at what lives
after the current 4 pages we use, I can't see too much important (mostly
it's d3d related), but there are a couple of things which look scary. I
am hopeful this can explain some of our odd HSW failures.

v2: Make the context only 17 pages. The power context space isn't used
ever, and execlists aren't used in our driver, making the actual total
66944 bytes.

v3: Add a comment to the code. (Jesse & Paulo)

Reported-by: "Azad, Vinit" <vinit.azad@intel.com>
Cc: stable@vger.kernel.org
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:54 +02:00
Ville Syrjälä 921c3b677b drm/i915: Fix VLV sprite register offsets
We forgot to add VLV_DISPLAY_BASE to the VLV sprite registers, which
caused the sprites to not work at all.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:53 +02:00
Ville Syrjälä 2af2c4909b Revert "drm/i915: Don't use the HDMI port color range bit on Valleyview"
The PIPECONF color range bit doesn't appear to be effective, on HDMI
outputs at least. The color range bit in the port register works though,
so let's use it.

I have not yet verified whether the PIPECONF bit works on DP outputs.

This reverts commit 83a2af88f8.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:53 +02:00
Ville Syrjälä 4abb2c3981 drm/i915: s/LFP/LPF in DPIO PLL register names
LPF is short for "low pass filter".

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:52 +02:00
Ville Syrjälä 99750bd46f drm/i915: Fix VLV PLL LPF coefficients for DAC
The current PLL settings produce a rather unstable picture when
I hook up a VLV to my HP ZR24w display via a VGA cable.

According to VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_9, we should
use the the same LPF coefficients for DAC as we do for HDMI and RBR DP.
And indeed that seems to cure the shivers.

v2: Add the name of the relevant document to the commit message

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:51 +02:00
Ville Syrjälä 7425034a33 drm/i915: Jump to at least RPe on VLV when increasing the GPU frequency
If the current GPU frquency is below RPe, and we're asked to increase
it, just go directly to RPe. This should provide better performance
faster than letting the frequency trickle up in response to the up
threshold interrupts.

For now just do it for VLV, since that matches quite closely how VLV
used to operate when the rps delayed timer kept things at RPe always.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:51 +02:00
Ville Syrjälä 6dc5848899 drm/i915: Don't increase the GPU frequency from the delayed VLV rps timer
There's little point in increasing the GPU frequency from the delayed
rps work on VLV. Now when the GPU is idle, the GPU frequency actually
keeps dropping gradually until it hits the minimum, whereas previously
it just ping-ponged constantly between RPe and RPe-1.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:50 +02:00
Ville Syrjälä 7a67092a25 drm/i915: GEN6_RP_INTERRUPT_LIMITS doesn't seem to exist on VLV
I can't find GEN6_RP_INTERRUPT_LIMITS (0xA014) anywhere in VLV docs.
Reading it always returns zero from what I can tell, and eliminating
it doesn't seem to make any difference to the behaviour of the system.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:49 +02:00
Ville Syrjälä d8289c9e7b drm/i915: Make the rps new_delay comparison more readable
Eliminate the weird inverted logic from the rps new_delay comparison.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:48 +02:00
Ville Syrjälä 80814ae4da drm/i915: Don't wait for Punit after each freq change on VLV
It seems that even though Punit reports the frequency change to have
been completed, it still reports the old frequency in the status
register for some time.

So rather than polling for Punit to complete the frequency change after
each request, poll before. This gets rid of the spurious "Punit overrode
GPU freq" messages.

This also lets us continue working while Punit is performing the actual
frequency change. As a result, openarena demo088-test1 timedemo average
fps is increased by ~5 fps, and the slowest frame duration is reduced
by ~25%.

The sysfs cur_freq file always reads the current frequency from Punit
anyway, so having rps.cur_delay be slightly off at times doesn't matter.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:48 +02:00
Ville Syrjälä 73008b989f drm/i915: Clean up VLV rps code a bit
Always print both the MHz value and raw register value for rps stuff.

Also kill a somewhat pointless local 'rpe' variable and just use
dev_priv->rps.rpe_delay.

While at it clean up the caps in "GPU" and "Punit" debug messages.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:47 +02:00
Chris Wilson a35cdaa0e1 drm/i915: Detect invalid scanout pitches
Report back the user error of attempting to setup a CRTC with an invalid
framebuffer pitch. This is trickier than it should be as on gen4, there
is a restriction that tiled surfaces must have a stride less than 16k -
which is less than the largest supported CRTC size.

v2: Fix the limits for gen3
v3: Move check into intel_framebuffer_init() and fix VLV limits. (vsyrjala)
v4: Use idiomatic '>=' for generation checks

References: https://bugs.freedesktop.org/show_bug.cgi?id=65099
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:46 +02:00
Ville Syrjälä e4e9222d4b drm/i915: Remove duplicated WaForceL3Serialization:vlv
No need to apply WaForceL3Serialization:vlv twice.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:46 +02:00
Daniel Vetter bf67dfeb68 drm/i915: don't scream into dmesg when a modeset fails
There are legit cases, e.g. when userspace asks for something
impossible. So tune it down to debug output like we do with all other
userspace-triggerable warnings.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=66111#c5
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
[danvet: Rebased.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:45 +02:00
Daniel Vetter 4f7fd7095d drm/i915: Fix up sdvo hpd pins for i965g/gm
Bspec seems to be full of lies, at least it disagress with reality:
Two systems corrobated that SDVO hpd bits are the same as on gen3.

v2: Update comment a bit.

Cc: Arthur Ranyan <arthur.j.runyan@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Reported-and-tested-by: Alex Fiestas <afiestas@kde.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58405
Cc: stable@vger.kernel.org
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:44 +02:00
Damien Lespiau f5adf94e5f drm/i915: Introduce an HAS_IPS() macro
Follow the trend and don't code conditions with platforms but with
features.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:44 +02:00
Jani Nikula 3765f30486 drm/i915: fix build warning on format specifier mismatch
drivers/gpu/drm/i915/i915_gem.c: In function ‘i915_gem_object_bind_to_gtt’:
drivers/gpu/drm/i915/i915_gem.c:3002:3: warning: format ‘%ld’ expects
argument of type ‘long int’, but argument 5 has type ‘size_t’ [-Wformat]

v2: Use %zu instead of %d. Two char patch, and 100% wrong. (Ville)

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:43 +02:00
Daniel Vetter 0f4f7b5795 drm/i915: tune down DIDL warning about too many outputs
Nothing the user (nor we) really can do about this, but upsets a nice
quiet boot.

Note that this happens mostly on SDVs where OEMs obviously haven't had
a chance yet to appropriately trim the output list.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=65988
Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>
[danvet: Amend commit message a bit to clarify a question from Paulo.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:42 +02:00
Konrad Rzeszutek Wilk 1625e7e549 drm/i915: make compact dma scatter lists creation work with SWIOTLB backend.
Git commit 90797e6d1e
("drm/i915: create compact dma scatter lists for gem objects") makes
certain assumptions about the under laying DMA API that are not always
correct.

On a ThinkPad X230 with an Intel HD 4000 with Xen during the bootup
I see:

[drm:intel_pipe_set_base] *ERROR* pin & fence failed
[drm:intel_crtc_set_config] *ERROR* failed to set mode on [CRTC:3], err = -28

Bit of debugging traced it down to dma_map_sg failing (in
i915_gem_gtt_prepare_object) as some of the SG entries were huge (3MB).

That unfortunately are sizes that the SWIOTLB is incapable of handling -
the maximum it can handle is a an entry of 512KB of virtual contiguous
memory for its bounce buffer. (See IO_TLB_SEGSIZE).

Previous to the above mention git commit the SG entries were of 4KB, and
the code introduced by above git commit squashed the CPU contiguous PFNs
in one big virtual address provided to DMA API.

This patch is a simple semi-revert - were we emulate the old behavior
if we detect that SWIOTLB is online. If it is not online then we continue
on with the new compact scatter gather mechanism.

An alternative solution would be for the the '.get_pages' and the
i915_gem_gtt_prepare_object to retry with smaller max gap of the
amount of PFNs that can be combined together - but with this issue
discovered during rc7 that might be too risky.

Reported-and-Tested-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
CC: Chris Wilson <chris@chris-wilson.co.uk>
CC: Imre Deak <imre.deak@intel.com>
CC: Daniel Vetter <daniel.vetter@ffwll.ch>
CC: David Airlie <airlied@linux.ie>
CC: <dri-devel@lists.freedesktop.org>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:42 +02:00
Rui Guo 6a9c4b35e6 drm/i915: Fix PCH detect with multiple ISA bridges in VM
In some virtualized environments (e.g. XEN), there is irrelevant ISA bridge in
the system. To work reliably, we should scan trhough all the ISA bridge
devices and check for the first match, instead of only checking the first one.

Signed-off-by: Rui Guo <firemeteor@users.sourceforge.net>
[danvet: Fixup conflict with the num_pch_pll removal. And add
subsystem header to the commit message headline.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:41 +02:00
Paulo Zanoni 73845adf33 drm/i915: rename intel_dp_destroy to intel_dp_connector_destroy
Because it's the function that destroys the connector, not the
encoder. And we already have intel_dp_encoder_destroy.

This has annoyed me for a long time.

Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Zoltan Nyul <zoltan.nyul@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2013-07-01 11:14:41 +02:00
Dave Airlie f7d452f4fd Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-next
- Various fixes that make surviving concurrent piglit more possible.
- Buffer object deletion no longer synchronous
- Context/register initialisation updates that have been reported to
solve some stability issues (particularly on some problematic GF119
chips)
- Kernel side support for VP2 video decoding engines

* 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: (44 commits)
  drm/nvd0-/disp: handle case where display engine is missing/disabled
  drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4
  drm/nouveau/bsp/nv84: initial vp2 engine implementation
  drm/nouveau/vp/nv84: initial vp2 engine implementation
  drm/nouveau/core: xtensa engine base class implementation
  drm/nouveau/vdec: fork vp3 implementations from vp2
  drm/nouveau/core: move falcon class to engine/
  drm/nouveau/kms: don't fail if there's no dcb table entries
  drm/nouveau: remove limit on gart
  drm/nouveau/vm: perform a bar flush when flushing vm
  drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches
  drm/nvc8/gr: update initial register/context values
  drm/nvc4/gr: update initial register/context values
  drm/nvc1/gr: update initial register/context values
  drm/nvc3/gr: update initial register/context values
  drm/nvc0/gr: update initial register/context values
  drm/nvd9/gr: update initial register/context values
  drm/nve4/gr: update initial register/context values
  drm/nvc0-/gr: bump maximum gpc/tpc limits
  drm/nvf0/gr: initial register/context setup
  ...
2013-07-01 14:10:20 +10:00
Maarten Lankhorst 791dc143ed drm/nvd0-/disp: handle case where display engine is missing/disabled
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:50 +10:00
Ben Skeggs e99716f13d drm/gr/nvc0-: merge nvc0/nve0 ucode, and use cpp instead of m4
No code changes, proven by envyas producing identical binaries.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:50 +10:00
Ilia Mirkin 05f9a5bc58 drm/nouveau/bsp/nv84: initial vp2 engine implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:49 +10:00
Ilia Mirkin a0376b1481 drm/nouveau/vp/nv84: initial vp2 engine implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:49 +10:00
Ilia Mirkin 44b1e3bd6a drm/nouveau/core: xtensa engine base class implementation
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:48 +10:00
Ilia Mirkin 0d4a1450c9 drm/nouveau/vdec: fork vp3 implementations from vp2
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:48 +10:00
Ben Skeggs a0fd4ec8f1 drm/nouveau/core: move falcon class to engine/
Not really "core" per-se.  About to merge Ilia's work adding another
similar class for the VP2 xtensa engines, so, seems like a good time to
move all these to engine/.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:47 +10:00
Ben Skeggs d2898713fb drm/nouveau/kms: don't fail if there's no dcb table entries
Fixes module not loading on Tesla K20.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:46 +10:00
Maarten Lankhorst 79442c3af0 drm/nouveau: remove limit on gart
Most graphics cards nowadays have a multiple of this limit as their vram,
so limiting GART doesn't seem to make much sense.

Signed-off-by: Maarten >Lnkhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:43 +10:00
Maarten Lankhorst 36798b61ed drm/nouveau/vm: perform a bar flush when flushing vm
Appears to fix the regression from "drm/nvc0/vm: handle bar tlb flushes
internally".

nvidia always seems to do this flush after writing values.

Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:42 +10:00
Ben Skeggs 57f0ec159b drm/nvc0/gr: cleanup register lists, and add nvce/nvcf to switches
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:41 +10:00
Ben Skeggs eb12f57be6 drm/nvc8/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:41 +10:00
Ben Skeggs dba50728fd drm/nvc4/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:40 +10:00
Ben Skeggs 58ef23056a drm/nvc1/gr: update initial register/context values
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2013-07-01 13:50:40 +10:00