Commit graph

5 commits

Author SHA1 Message Date
Kumar Gala 2e56ff206b [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime
Make it so we do a runtime check to know if we need to write cfg_addr
as big or little endian.  This is needed if we want to allow 86xx support
to co-exist in the same kernel as other 6xx PPCs.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-07-23 22:29:09 -05:00
Kumar Gala dbf8471f52 [POWERPC] Merge ppc32 and ppc64 pcibios_alloc_controller() prototypes
Make the ppc32 pcibios_alloc_controller take a device node to match
the ppc64 prototypes and have it set arch_data.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-06-29 01:58:39 -05:00
Kumar Gala 0a3786c5f7 [POWERPC] Removed remnants of bus_offset
Removed the remants of bus_offset and use self_busno in the mv64x60 case
and use pci_assign_all_buses on 83xx/85xx.

83xx/85xx have multiple PHBs and the firmwares on these devices tend not
to handle topologies with P2P bridges well so we let Linux just reassign
the bus numbers to match.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-06-29 01:58:15 -05:00
Kumar Gala 5ab9c4524d [POWERPC] Remove set_cfg_type for PCI indirect users that don't need it
The Freescale and Marvell PCI controllers dont require explicit setting for
type 1 config cycles.  They handle producing them by implicitly looking at the
bus, devfn.

The TSI108 and 52xx don't use the generic PCI indirect code and thus don't
bother with set_cfg_type.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2007-06-29 01:57:07 -05:00
Dale Farnsworth e1a3107b06 [POWERPC] Add Marvell mv64x60 PCI bridge support
This patch adds PCI bridge support for the Marvell mv64x60 chip.
We also provide the ability to read/write the mv64x60 hotswap
register via sysfs if the hs_reg_valid property is set in the
device tree.

Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Paul Mackerras <paulus@samba.org>
2007-05-12 11:32:50 +10:00