Add new macros for describing pins without GPIO functionality:
- NOGP_ALL() expands to a list of PIN_id values, to be used for
generating symbolic enum values,
- PINMUX_NOGP_ALL() expands to a list of sh_pfc_pin entries, to
list all pins and their capabilities.
Both macros depend on an SoC-specific CPU_ALL_NOGP() macro, to be
provided by each individual SoC pin control driver.
The new macros offer two advantages over the existing SH_PFC_PIN_NAMED()
and SH_PFC_PIN_NAMED_CFG() macros:
1. They do not rely on PIN_NUMBER() macros and physical pin numbering,
hence do not suffer from pin numbering confusion among different
SoC/SiP packages.
2. They are similar in spirit to the existing scheme for handling pins
with GPIO functionality.
Note that internal to the driver, non-GPIO pins use a sequential
numbering scheme which starts after the highest GPIO pin number in use.
This value is calculated automatically, using two new helper macros, for
systems with either 32-port bank (GP port style) or linear (PORT style)
pin space. Sample expansion:
GP_LAST = sizeof(union {
char dummy[0] __attribute__((deprecated, deprecated));
char GP_0_0[(0 * 32) + 0] __attribute__((deprecated, deprecated));
char GP_0_1[(0 * 32) + 1] __attribute__((deprecated, deprecated));
...
char GP_7_3[(7 * 32) + 3] __attribute__((deprecated, deprecated));
})
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Get rid of the custom PORT_GP_PUP_27() macro by using the common
PORT_GP_CFG_27() macro instead.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
This follows the style of the existing PORT_GP_X macros, and will be
used by a follow-up patch for the r8a7778 SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car M3-N SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on the R-Car M3-W and RZ/G2M SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on revisions ES2.x and later of the R-Car H3 SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Add pins, groups and functions for the 16-Bit Timer Pulse Unit outputs
on revision ES1.x of the R-Car H3 SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Hardware Manual Errata for rev. 1.50 of March 26, 2019 removed the bit
definitions for MMC_CD and MMC_WP in the documentation for the IPSR6 and
IPSR7 registers, as these pin functionalities do not exist on R-Car
V3M.
Remove the definitions, and the corrresponding pins and groups.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Several drivers have identical definitions for PIN_NONE.
Provide a definition with a SH_PFC_ prefix for general use in sh_pfc.h,
and convert all drivers over to use it.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
It is very common for a pin to support both pull-up and pull-down
functionality. Hence add a shorthand SH_PFC_PIN_CFG_PULL_UP_DOWN.
This not only reduces typing, but also avoids the need for several line
breaks, and makes many overly long lines shorter, improving
readability.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
There are two variants of the CPU_ALL_PORT() macro in use:
1. A three-parameter variant, to be provided for SoCs with a linear
GPIO pin space ("PORT style"),
2. A two-parameter variant, to be provided for SoCs with 32-port GPIO
banks ("GP port style").
Rename the 2-parameter variant to CPU_ALL_GP(), to avoid confusion, and
to increase naming consistency.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Extend the run-time debug code with checks to ensure there are no
conflicting pin names, numbers, or enumeration values.
This helps catching bugs early.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
The pinmux groups and functions arrays may contain two parts, to ease
supporting SoCs that expose pin subsets of other related SoCs. Both
parts need to be declared with explicit sizes, which thus need to be
updated when adding support for more groups and functions.
If a size is too small, the compiler will detect this at build time
("excess elements in array initializer").
If a size is too large, this may go undetected (for pin groups), lead to
pin controller registration failures (for pin functions: "pinmux ops has
no name for functionN"), or crash the optional run-time debug code (for
pin groups).
Extend the run-time debug code with checks to detect this, to help
catching bugs early.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
All run-time debug code is called from sh_pfc_init(), which is __init.
Fixes: 6161b39a14 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Improve wording while at it.
Fixes: 6161b39a14 ("pinctrl: sh-pfc: Validate pinmux tables at runtime when debugging")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
- Document (kerneldoc) core mfd_add_devices() API
- New Drivers
- Add support for Altera SOCFPGA System Manager
- Add support for Maxim MAX77650/77651 PMIC
- Add support for Maxim MAX77663 PMIC
- Add support for ST Multi-Function eXpander (STMFX)
- New Device Support
- Add support for LEDs to Intel Cherry Trail Whiskey Cove PMIC
- Add support for RTC to SAMSUNG Electronics S2MPA01 PMIC
- Add support for SAM9X60 to Atmel HLCDC (High-end LCD Controller)
- Add support for USB X-Powers AXP 8xx PMICs
- Add support for Integrated Sensor Hub (ISH) to ChromeOS EC
- Add support for USB PD Logger to ChromeOS EC
- Add support for AXP223 to X-Powers AXP series PMICs
- Add support for Power Supply to X-Powers AXP 803 PMICs
- Add support for Comet Lake to Intel Low Power Subsystem
- Add support for Fingerprint MCU to ChromeOS EC
- Add support for Touchpad MCU to ChromeOS EC
- Move TI LM3532 support to LED
- New Functionality
- Add/extend DT support; max77650, max77620
- Add support for power-off; max77620
- Add support for clocking; syscon
- Add support for host sleep event; cros_ec
- Fix-ups
- Trivial; Formatting, spelling, etc; Kconfig, sec-core, ab8500-debugfs
- Remove unused functionality; rk808, da9063-*
- SPDX conversion; da9063-*, atmel-*,
- Adapt/add new register definitions; cs47l35-tables, cs47l90-tables, imx6q-iomuxc-gpr
- Fix-up DT bindings; ti-lmu, cirrus,lochnagar
- Simply obtaining driver data; ssbi, t7l66xb, tc6387xb, tc6393xb
- Bug Fixes
- Fix incorrect defined values; max77620, da9063
- Fix device initialisation; twl6040
- Reset device on init; intel-lpss
- Fix build warnings when !OF; sun6i-prcm
- Register OF match tables; tps65912-spi
- Fix DMI matching; intel_quark_i2c_gpio
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Merge tag 'mfd-next-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd
Pull MFD updates from Lee Jones:
"Core Framework:
- Document (kerneldoc) core mfd_add_devices() API
New Drivers:
- Altera SOCFPGA System Manager
- Maxim MAX77650/77651 PMIC
- Maxim MAX77663 PMIC
- ST Multi-Function eXpander (STMFX)
New Device Support:
- LEDs support in Intel Cherry Trail Whiskey Cove PMIC
- RTC support in SAMSUNG Electronics S2MPA01 PMIC
- SAM9X60 support in Atmel HLCDC (High-end LCD Controller)
- USB X-Powers AXP 8xx PMICs
- Integrated Sensor Hub (ISH) in ChromeOS EC
- USB PD Logger in ChromeOS EC
- AXP223 in X-Powers AXP series PMICs
- Power Supply in X-Powers AXP 803 PMICs
- Comet Lake in Intel Low Power Subsystem
- Fingerprint MCU in ChromeOS EC
- Touchpad MCU in ChromeOS EC
- Move TI LM3532 support to LED
New Functionality:
- max77650, max77620: Add/extend DT support
- max77620 power-off
- syscon clocking
- croc_ec host sleep event
Fix-ups:
- Trivial; Formatting, spelling, etc; Kconfig, sec-core, ab8500-debugfs
- Remove unused functionality; rk808, da9063-*
- SPDX conversion; da9063-*, atmel-*,
- Adapt/add new register definitions; cs47l35-tables, cs47l90-tables, imx6q-iomuxc-gpr
- Fix-up DT bindings; ti-lmu, cirrus,lochnagar
- Simply obtaining driver data; ssbi, t7l66xb, tc6387xb, tc6393xb
Bug Fixes:
- Fix incorrect defined values; max77620, da9063
- Fix device initialisation; twl6040
- Reset device on init; intel-lpss
- Fix build warnings when !OF; sun6i-prcm
- Register OF match tables; tps65912-spi
- Fix DMI matching; intel_quark_i2c_gpio"
* tag 'mfd-next-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (65 commits)
mfd: Use dev_get_drvdata() directly
mfd: cros_ec: Instantiate properly CrOS Touchpad MCU device
mfd: cros_ec: Instantiate properly CrOS FP MCU device
mfd: cros_ec: Update the EC feature codes
mfd: intel-lpss: Add Intel Comet Lake PCI IDs
mfd: lochnagar: Add links to binding docs for sound and hwmon
mfd: ab8500-debugfs: Fix a typo ("deubgfs")
mfd: imx6sx: Add MQS register definition for iomuxc gpr
dt-bindings: mfd: LMU: Fix lm3632 dt binding example
mfd: intel_quark_i2c_gpio: Adjust IOT2000 matching
mfd: da9063: Fix OTP control register names to match datasheets for DA9063/63L
mfd: tps65912-spi: Add missing of table registration
mfd: axp20x: Add USB power supply mfd cell to AXP803
mfd: sun6i-prcm: Fix build warning for non-OF configurations
mfd: intel-lpss: Set the device in reset state when init
platform/chrome: Add support for v1 of host sleep event
mfd: cros_ec: Add host_sleep_event_v1 command
mfd: cros_ec: Instantiate the CrOS USB PD logger driver
mfd: cs47l90: Make DAC_AEC_CONTROL_2 readable
mfd: cs47l35: Make DAC_AEC_CONTROL_2 readable
...
drivers/pinctrl/pinctrl-stmfx.c:441 stmfx_pinctrl_irq_set_type() warn: bitwise AND condition is false here
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
smatch warnings:
drivers/pinctrl/pinctrl-stmfx.c:225 stmfx_pinconf_get() warn: unsigned 'dir' is never less than zero.
drivers/pinctrl/pinctrl-stmfx.c:228 stmfx_pinconf_get() warn: unsigned 'type' is never less than zero.
drivers/pinctrl/pinctrl-stmfx.c:231 stmfx_pinconf_get() warn: unsigned 'pupd' is never less than zero.
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Core changes:
- The gpiolib MMIO driver has been enhanced to handle two direction
registers, i.e. one register to set lines as input and one register
to set lines as output. It turns out some silicon engineer thinks
the ability to configure a line as input and output at the same
time makes sense, this can be debated but includes a lot of analog
electronics reasoning, and the registers are there and need to
be handled consistently. Unsurprisingly, we enforce the lines to
be either inputs or outputs in such schemes.
- Send in the proper argument value to .set_config() dispatched to
the pin control subsystem. Nobody used it before, now someone
does, so fix it to work as expected.
- The ACPI gpiolib portions can now handle pin bias setting (pull up
or pull down). This has been in the ACPI spec for years and we
finally have it properly integrated with Linux GPIOs. It was based
on an observation from Andy Schevchenko that Thomas Petazzoni's
changes to the core for biasing the PCA950x GPIO expander actually
happen to fit hand-in-glove with what the ACPI core needed.
Such nice synergies happen sometimes.
New drivers:
- A new driver for the Mellanox BlueField GPIO controller. This is
using 64bit MMIO registers and can configure lines as inputs
and outputs at the same time and after improving the MMIO library
we handle it just fine. Interesting.
- A new IXP4xx proper gpiochip driver with hierarchical interrupts
should be coming in from the ARM SoC tree as well.
Driver enhancements:
- The PCA053x driver handles the CAT9554 GPIO expander.
- The PCA053x driver handles the NXP PCAL6416 GPIO expander.
- Wake-up support on PCA053x GPIO lines.
- OMAP now does a nice asynchronous IRQ handling on wake-ups by
letting everything wake up on edges, and this makes runtime PM
work as expected too.
Misc:
- Several cleanups such as devres fixes.
- Get rid of some languager comstructs that cause problems when
compiling with LLVMs clang.
- Documentation review and update.
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Merge tag 'gpio-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio
Pull gpio updates from Linus Walleij:
"This is the bulk of the GPIO changes for the v5.2 kernel cycle. A bit
later than usual because I was ironing out my own mistakes. I'm
holding some stuff back for the next kernel as a result, and this
should be a healthy and well tested batch.
Core changes:
- The gpiolib MMIO driver has been enhanced to handle two direction
registers, i.e. one register to set lines as input and one register
to set lines as output. It turns out some silicon engineer thinks
the ability to configure a line as input and output at the same
time makes sense, this can be debated but includes a lot of analog
electronics reasoning, and the registers are there and need to be
handled consistently. Unsurprisingly, we enforce the lines to be
either inputs or outputs in such schemes.
- Send in the proper argument value to .set_config() dispatched to
the pin control subsystem. Nobody used it before, now someone does,
so fix it to work as expected.
- The ACPI gpiolib portions can now handle pin bias setting (pull up
or pull down). This has been in the ACPI spec for years and we
finally have it properly integrated with Linux GPIOs. It was based
on an observation from Andy Schevchenko that Thomas Petazzoni's
changes to the core for biasing the PCA950x GPIO expander actually
happen to fit hand-in-glove with what the ACPI core needed. Such
nice synergies happen sometimes.
New drivers:
- A new driver for the Mellanox BlueField GPIO controller. This is
using 64bit MMIO registers and can configure lines as inputs and
outputs at the same time and after improving the MMIO library we
handle it just fine. Interesting.
- A new IXP4xx proper gpiochip driver with hierarchical interrupts
should be coming in from the ARM SoC tree as well.
Driver enhancements:
- The PCA053x driver handles the CAT9554 GPIO expander.
- The PCA053x driver handles the NXP PCAL6416 GPIO expander.
- Wake-up support on PCA053x GPIO lines.
- OMAP now does a nice asynchronous IRQ handling on wake-ups by
letting everything wake up on edges, and this makes runtime PM work
as expected too.
Misc:
- Several cleanups such as devres fixes.
- Get rid of some languager comstructs that cause problems when
compiling with LLVMs clang.
- Documentation review and update"
* tag 'gpio-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-gpio: (85 commits)
gpio: Update documentation
docs: gpio: convert docs to ReST and rename to *.rst
gpio: sch: Remove write-only core_base
gpio: pxa: Make two symbols static
gpiolib: acpi: Respect pin bias setting
gpiolib: acpi: Add acpi_gpio_update_gpiod_lookup_flags() helper
gpiolib: acpi: Set pin value, based on bias, more accurately
gpiolib: acpi: Change type of dflags
gpiolib: Introduce GPIO_LOOKUP_FLAGS_DEFAULT
gpiolib: Make use of enum gpio_lookup_flags consistent
gpiolib: Indent entry values of enum gpio_lookup_flags
gpio: pca953x: add support for pca6416
dt-bindings: gpio: pca953x: document the nxp,pca6416
gpio: pca953x: add pcal6416 to the of_device_id table
gpio: gpio-omap: Remove conditional pm_runtime handling for GPIO interrupts
gpio: gpio-omap: configure edge detection for level IRQs for idle wakeup
tracing: stop making gpio tracing configurable
gpio: pca953x: Configure wake-up path when wake-up is enabled
gpio: of: Optimize quirk checks
gpio: mmio: Drop bgpio_dir_inverted
...
module_i2c_driver and pinconf_generic_dt_node_to_map_pin are undeclared
if CONFIG_I2C and CONFIG_OF are not enabled.
Fixes: 1490d9f841 ("pinctrl: Add STMFX GPIO expander Pinctrl/GPIO driver")
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
This patch adds pinctrl/GPIO driver for STMicroelectronics
Multi-Function eXpander (STMFX) GPIO expander.
STMFX is an I2C slave controller, offering up to 24 GPIOs.
The driver relies on generic pin config interface to configure the GPIOs.
Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
It is expected that some of these operations won't work on each and
every HW. Previously, even a simple `cat
/sys/kernel/debug/pinctrl/spi1.1/pinconf-pins` caused excessive dmesg
output.
Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Cc: Phil Reid <preid@electromag.com.au>
Cc: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Non-critical fixes for Intel Baytrail and Intel Cedarfork.
Couple of fixes for all pinctrl-intel based drivers with regard to
IRQ handling, i.e. moving PM calls to noirq level to avoid IRQ lose
and restore ownership of pins to prevent IRQ masking side effect.
The following is an automated git shortlog grouped by driver:
baytrail:
- Fix potential NULL pointer dereference
cedarfork:
- Update pin names according to v1.13c
intel:
- Increase readability of intel_gpio_update_pad_mode()
- Retain HOSTSW_OWN for requested gpio pin
- move gpio suspend/resume to noirq phase
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Merge tag 'intel-pinctrl-v5.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel
intel-pinctrl for v5.2-1
Non-critical fixes for Intel Baytrail and Intel Cedarfork.
Couple of fixes for all pinctrl-intel based drivers with regard to
IRQ handling, i.e. moving PM calls to noirq level to avoid IRQ lose
and restore ownership of pins to prevent IRQ masking side effect.
The following is an automated git shortlog grouped by driver:
baytrail:
- Fix potential NULL pointer dereference
cedarfork:
- Update pin names according to v1.13c
intel:
- Increase readability of intel_gpio_update_pad_mode()
- Retain HOSTSW_OWN for requested gpio pin
- move gpio suspend/resume to noirq phase
Make the BM1880 SoC pinctrl driver depend on COMPILE_TEST to get compiler
test coverage and also select this driver by default for ARCH_BITMAIN
platform.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add pinctrl support for Bitmain BM1880 SoC. The driver only handles
pinmuxing as the SoC is not capable of handling pinconf.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
It is not guaranteed that the IRQ controller driver is probed before
the pin controller driver gets probed.
Considering this, check for the irq domain availability during probe
and return EPROBE_DEFER if needed.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit adds the pinctrl driver for the MediaTek's MT8516 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
Acked-by: Sean Wang <sean.wang@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The call to of_parse_phandle returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
Detected by coccinelle with the following warnings:
./drivers/pinctrl/zte/pinctrl-zx.c:415:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.
./drivers/pinctrl/zte/pinctrl-zx.c:422:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.
./drivers/pinctrl/zte/pinctrl-zx.c:436:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.
./drivers/pinctrl/zte/pinctrl-zx.c:444:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.
./drivers/pinctrl/zte/pinctrl-zx.c:448:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 407, but without a corresponding object release within this function.
Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Jun Nie <jun.nie@linaro.org>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We better to use usual pattern for read-modify-update,
than doing some operations in definition block.
No functional change.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The touchpad of the ASUS laptops E403NA, X540NA, X541NA are not
responsive after suspend/resume. The following error message
shows after resume.
i2c_hid i2c-ELAN1200:00: failed to reset device.
On these laptops, the touchpad interrupt is connected via a GPIO
pin which is controlled by Intel pinctrl. After system resumes,
the GPIO is in ACPI mode and no longer works as an IRQ.
This commit saves the HOSTSW_OWN value during suspend, make sure
the HOSTSW_OWN mode remains the same after resume.
Signed-off-by: Chris Chiu <chiu@endlessm.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
The call to of_get_child_by_name returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
Detected by coccinelle with the following warnings:
./drivers/pinctrl/pinctrl-pistachio.c:1422:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1360, but without a corresponding object release within this function.
Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
H6 SoC has a "pio group withstand voltage mode" register (datasheet
description), that needs to be used to select either 1.8V or 3.3V I/O mode,
based on what voltage is powering the respective pin banks and is thus used
for I/O signals.
Add support for configuring this register according to the voltage of the
pin bank regulator (if enabled).
This is similar to the support for I/O bias voltage setting patch for A80
and the same concerns apply. See:
commit 402bfb3c13 ("Support I/O bias voltage setting on A80")
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
H6 has a different I/O voltage bias setting method than A80. Prepare
existing code for using alternative bias voltage setting methods.
Signed-off-by: Ondrej Jirman <megous@megous.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The call to of_get_child_by_name returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
Detected by coccinelle with the following warnings:
./drivers/pinctrl/pinctrl-st.c:1188:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function.
./drivers/pinctrl/pinctrl-st.c:1188:3-9: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function.
./drivers/pinctrl/pinctrl-st.c:1199:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function.
./drivers/pinctrl/pinctrl-st.c:1199:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 1175, but without a corresponding object release within this function.
Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-gpio@vger.kernel.org
Cc: linux-kernel@vger.kernel.org (open list)
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The call to of_find_compatible_node returns a node pointer with refcount
incremented thus it must be explicitly decremented after the last
usage.
Detected by coccinelle with the following warnings:
./drivers/pinctrl/samsung/pinctrl-exynos-arm.c:76:2-8: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 66, but without a corresponding object release within this function.
./drivers/pinctrl/samsung/pinctrl-exynos-arm.c:82:1-7: ERROR: missing of_node_put; acquired a node pointer with refcount incremented on line 66, but without a corresponding object release within this function.
Signed-off-by: Wen Yang <wen.yang99@zte.com.cn>
Cc: Linus Walleij <linus.walleij@linaro.org>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <s.nawrocki@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Align pins names with names provided in official stm32mp157 datasheet
available on st.com.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
A same SoC can be available in several packages. Differences between
packages are only the numbers of available balls. In order not to write
a driver for each new package, same driver (ex: pinctrl-stm32mp157.c) will
be used. This patch introduces the "package" property for each pin. So on a
same driver, it will be possible to indicate on which package the pin is
available. The package information will be got from the device tree.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
To support pinctl hog restore after LPSR resume back,
add the generic suspend/resume in pinctrl-imx along with the
generic pm ops to be used by platform specific drivers. Then
make use of the newly added ops in i.MX8MQ platform specific
driver.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The pincontrol callbacks used to be symmetric:
enable/disable.
However for a while we only have one function that
set the muxing, no disabling.
Drop the unused disable function, and rename the
*enable() function to *set().
Reported-by: Nathan Chancellor <natechancellor@gmail.com>
Cc: YueHaibing <yuehaibing@huawei.com>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
In current driver, SET_LATE_SYSTEM_SLEEP_PM_OPS is used to install the
callbacks for suspend/resume.
GPIO pin may be used as the interrupt pin by some device. However, using
SET_LATE_SYSTEM_SLEEP_PM_OPS() to install the callbacks, the resume
callback is called after resume_device_irqs(). Unintended interrupts may
arrive due to resuming device irqs first, but the GPIO controller is not
properly restored.
Normally, for a SMP system, there are multiple cores, so even when there are
unintended interrupts, BSP gets the chance to initialize the GPIO chip soon.
But when there is only 1 core is active (other cores are offlined or
single core) during resume, it is more easily to observe the unintended
interrupts.
This patch renames the suspend/resume function by adding suffix "_noirq",
and installs the callbacks using SET_NOIRQ_SYSTEM_SLEEP_PM_OPS().
Signed-off-by: Binbin Wu <binbin.wu@intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Some of the AMD reference boards used single GPIO line for
multiple devices. So added IRQF_SHARED flag in amd pinctrl driver.
Signed-off-by: Sandeep Singh <Sandeep.Singh@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
cc: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Mukesh Ojha <mojha@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The address of "ipctl->pin_regs[pin_id]" can't be NULL. It's the offset
into an array in the middle of a struct. This patch removes the check.
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Acked-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This patch provides the advanced drive for I2C used pins on MT8183.
The detail strength specification description of the I2C pin:
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
For I2C pins, there are existing generic driving setup and the above
specific driving setup. I2C pins can only support 2/4/6/8/10/12/14/16mA
driving adjustment in generic driving setup. But in specific driving
setup, they can support 0.125/0.25/0.5/1mA adjustment.
If we enable specific driving setup for I2C pins,
the existing generic driving setup will be disabled.
For some special features, we need the I2C pins specific driving setup.
The specific driving setup is controlled by E1E0EN.
So we need add extra vendor driving preperty instead of the generic
driving property. We can add "mediatek,drive-strength-adv = <XXX>;"
to describe the specific driving setup property.
"XXX" means the value of E1E0EN. So the valid arguments of
"mediatek,drive-strength-adv" are from 0 to 7.
Signed-off-by: Zhiyong Tao <zhiyong.tao@mediatek.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
axp20x_build_funcs_groups allocates groups via devm_kcalloc and tries to
dereference without checking for NULL. This patch avoids such a
scenario.
Signed-off-by: Aditya Pakki <pakki001@umn.edu>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The comment for this dbg_show says that it is supposed to return more
than what the generic code is showing, including de-glitching. That's
wrong because:
- this chip does not support deglitching,
- the code does not print anything extra compared to the generic
handler,
- its behavior is different because it skips unrequested GPIOs; the
generic code prints their names if they're assigned
There is an important difference, though. Previously, dbg_show would
re-check some registers to see if they still match what the regmap
thinks should be in there. This was semi-useful when develpoing the HW
board because it immediately pointed to SPI wiring problem if a CS
connection was missing (0xffs are easy to see). However, I do not think
that this makes much sense -- and one could always do this in some other
way if needed.
Signed-off-by: Jan Kundrát <jan.kundrat@cesnet.cz>
Cc: Phil Reid <preid@electromag.com.au>
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Fix sparse warnings:
drivers/pinctrl/pinctrl-artpec6.c:691:5: warning:
symbol 'artpec6_pmx_enable' was not declared. Should it be static?
drivers/pinctrl/pinctrl-artpec6.c:705:6: warning:
symbol 'artpec6_pmx_disable' was not declared. Should it be static?
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
Reviewed-by: Mukesh Ojha <mojha@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
- Add HSCIF (serial) pin groups on R-Car H1,
- Add I2C[035] pin groups on R-Car M3-N,
- Add CANFD pin groups on RZ/G2M and RZ/G2E,
- Retain SDHI/MMC clock return path delay configuration across
suspend/resume on R-Car Gen3,
- More validation of pinmux tables at build and runtime, including
compile-test coverage of all drivers,
- Small fixes, improvements, and cleanups.
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Merge tag 'sh-pfc-for-v5.2-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: sh-pfc: Updates for v5.2
- Add HSCIF (serial) pin groups on R-Car H1,
- Add I2C[035] pin groups on R-Car M3-N,
- Add CANFD pin groups on RZ/G2M and RZ/G2E,
- Retain SDHI/MMC clock return path delay configuration across
suspend/resume on R-Car Gen3,
- More validation of pinmux tables at build and runtime, including
compile-test coverage of all drivers,
- Small fixes, improvements, and cleanups.
This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.
These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
[takeshi.kihara.df: add blank lines after function declarations]
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[uli: use standard macros PINMUX_IPSR_PHYS and PINMUX_IPSR_PHYS_MSEL]
Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
