Allocate basic xHCI host controller data structures. For every xHC, there
is a command ring, an event ring, and a doorbell array.
The doorbell array is used to notify the host controller that work has
been enqueued onto one of the rings. The host controller driver enqueues
commands on the command ring. The HW enqueues command completion events
on the event ring and interrupts the system (currently using PCI
interrupts, although the xHCI HW will use MSI interrupts eventually).
All rings and the doorbell array must be allocated by the xHCI host
controller driver.
Each ring is comprised of one or more segments, which consists of 16-byte
Transfer Request Blocks (TRBs) that can be chained to form a Transfer
Descriptor (TD) that represents a multiple-buffer request. Segments are
linked into a ring using Link TRBs, which means they are dynamically
growable.
The producer of the ring enqueues a TD by writing one or more TRBs in the
ring and toggling the TRB cycle bit for each TRB. The consumer knows it
can process the TRB when the cycle bit matches its internal consumer cycle
state for the ring. The consumer cycle state is toggled an odd amount of
times in the ring.
An example ring (a ring must have a minimum of 16 TRBs on it, but that's
too big to draw in ASCII art):
chain cycle
bit bit
------------------------
| TD A TRB 1 | 1 | 1 |<------------- <-- consumer dequeue ptr
------------------------ | consumer cycle state = 1
| TD A TRB 2 | 1 | 1 | |
------------------------ |
| TD A TRB 3 | 0 | 1 | segment 1 |
------------------------ |
| TD B TRB 1 | 1 | 1 | |
------------------------ |
| TD B TRB 2 | 0 | 1 | |
------------------------ |
| Link TRB | 0 | 1 |----- |
------------------------ | |
| |
chain cycle | |
bit bit | |
------------------------ | |
| TD C TRB 1 | 0 | 1 |<---- |
------------------------ |
| TD D TRB 1 | 1 | 1 | |
------------------------ |
| TD D TRB 2 | 1 | 1 | segment 2 |
------------------------ |
| TD D TRB 3 | 1 | 1 | |
------------------------ |
| TD D TRB 4 | 1 | 1 | |
------------------------ |
| Link TRB | 1 | 1 |----- |
------------------------ | |
| |
chain cycle | |
bit bit | |
------------------------ | |
| TD D TRB 5 | 1 | 1 |<---- |
------------------------ |
| TD D TRB 6 | 0 | 1 | |
------------------------ |
| TD E TRB 1 | 0 | 1 | segment 3 |
------------------------ |
| | 0 | 0 | | <-- producer enqueue ptr
------------------------ |
| | 0 | 0 | |
------------------------ |
| Link TRB | 0 | 0 |---------------
------------------------
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Add PCI initialization code to take control of the xHCI host controller
away from the BIOS, halt, and reset the host controller. The xHCI spec
says that BIOSes must give up the host controller within 5 seconds.
Add some host controller glue functions to handle hardware initialization
and memory allocation for the host controller. The current xHCI
prototypes use PCI interrupts, but the xHCI spec requires MSI-X
interrupts. Add code to support MSI-X interrupts, but use the PCI
interrupts for now.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
This is the first of many patches to add support for USB 3.0 devices and
the hardware that implements the eXtensible Host Controller Interface
(xHCI) 0.95 specification. This specification is not yet publicly
available, but companies can receive a copy by becoming an xHCI
Contributor (see http://www.intel.com/technology/usb/xhcispec.htm).
No xHCI hardware has made it onto the market yet, but these patches have
been tested under the Fresco Logic host controller prototype.
This patch adds the xHCI register sets, which are grouped into five sets:
- Generic PCI registers
- Host controller "capabilities" registers (cap_regs) short
- Host controller "operational" registers (op_regs)
- Host controller "runtime" registers (run_regs)
- Host controller "doorbell" registers
These some of these registers may be virtualized if the Linux driver is
running under a VM. Virtualization has not been tested for this patch.
Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
