Fix mpc7448hpc2 tsi108 device_type bug.
Wrong device type will break the board startup.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fixed the following warnings:
WARNING: vmlinux.o(.text+0x2934): Section mismatch: reference to .init.text:__alloc_bootmem (between 'irq_alloc_host' and 'irq_set_default_host')
WARNING: vmlinux.o(.text+0xb2aa): Section mismatch: reference to .init.data:boot_command_line (between 'register_early_udbg_console' and 'udbg_printf')
WARNING: vmlinux.o(.text+0xb2b2): Section mismatch: reference to .init.data:boot_command_line (between 'register_early_udbg_console' and 'udbg_printf')
WARNING: vmlinux.o(.text+0xe354): Section mismatch: reference to .init.text:__alloc_bootmem (between 'pcibios_alloc_controller' and 'pci_domain_nr')
WARNING: vmlinux.o(.text+0x12768): Section mismatch: reference to .init.text:update_bridge_resource (between 'quirk_fsl_pcie_transparent' and 'indirect_read_config')
WARNING: vmlinux.o(.text+0x127a8): Section mismatch: reference to .init.text:update_bridge_resource (between 'quirk_fsl_pcie_transparent' and 'indirect_read_config')
WARNING: vmlinux.o(.text+0x17566c): Section mismatch: reference to .init.text:pcibios_fixup_bus (between 'pci_scan_child_bus' and 'pci_scan_bus_parented')
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The MPC8544 dts needed to set the new phy-connection-type to rgmii-id
for the Vitesse PHY on the board to work properly.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Freescale PCI PHBs actual report back values in the BAR registers
this causes issues in that we try to allocate resources for them
and will get error messages like the following on MPC8544 DS:
PCI: Failed to allocate mem resource #1:80000000@0 for 0000:00:00.0
To address this if we are class PCI_CLASS_PROCESSOR_POWERPC, a normal
header type, and the PHB we clear out all the resources.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We didn't actually propogate the flag we pass into setup_indirect_pci()
to set indirect_type and thus were getting the wrong endianness if
PPC_INDIRECT_TYPE_BIG_ENDIAN was set.
Also, we need to or in additional flags rather than just doing a
direct assignment.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We can't mark the whole thing init because there are dependencies
in bootloaders that assume that _start, or whatever the image
entry value, is 2 instructions before the "HdrS" signature.
In fact, TILO assumes this entry is always at 0x4000, yikes!
Also, right after the bootloader info area there are OBP strings and
values that get used later in the boot process, and those are not all
provably .init yet.
Signed-off-by: David S. Miller <davem@davemloft.net>
Sparc optimized memset (arch/sparc/lib/memset.S) does not fill last
byte of the memory area, if area size is less than 8 bytes and start
address is not word (4-bytes) aligned.
Here is code chunk where bug located:
/* %o0 - memory address, %o1 - size, %g3 - value */
8:
add %o0, 1, %o0
subcc %o1, 1, %o1
bne,a 8b
stb %g3, [%o0 - 1]
This code should write byte every loop iteration, but last time delay
instruction stb is not executed because branch instruction sets
"annul" bit.
Patch replaces bne,a by bne instruction.
Error can be reproduced by simple kernel module:
--------------------
#include <linux/module.h>
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/errno.h>
#include <string.h>
static void do_memset(void **p, int size)
{
memset(p, 0x00, size);
}
static int __init memset_test_init(void)
{
char fooc[8];
int *fooi;
memset(fooc, 0xba, sizeof(fooc));
do_memset((void**)(fooc + 3), 1);
fooi = (int*) fooc;
printk("%08X %08X\n", fooi[0], fooi[1]);
return -1;
}
static void __exit memset_test_cleanup(void)
{
return;
}
module_init(memset_test_init);
module_exit(memset_test_cleanup);
MODULE_LICENSE("GPL");
EXPORT_NO_SYMBOLS;
--------------------
Signed-off-by: Alexander Shmelev <ashmelev@task.sun.mcst.ru>
Signed-off-by: David S. Miller <davem@davemloft.net>
This fixes boot failures when the build-id LD option is
actually used, because without it we end up with multiple
PT_LOAD sections which the SILO boot loader cannot handle.
Signed-off-by: David S. Miller <davem@davemloft.net>
* 'request-queue-t' of git://git.kernel.dk/linux-2.6-block:
[BLOCK] Add request_queue_t and mark it deprecated
[BLOCK] Get rid of request_queue_t typedef
spufs.h now has two enums for the sched_flags leading to identical
values for SPU_SCHED_WAS_ACTIVE and SPU_SCHED_NOTIFY_ACTIVE. Merge
them into a single enum as they were in the IBM development tree.
Signed-off-by: Christoph Hellwig <hch@lst.de>
Acked-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2.6.23-rc1 turned up another batch of references from non-__init code to
__init code. In most cases, these were missing __init annotations. In one
case (os_drop_memory), the annotation was present but wrong.
init_maps is __init, but for some reason was being very careful about the
mechanism by which it allocated memory, checking whether it was OK to use
kmalloc (at this point in the boot, it definitely isn't) and using either
alloc_bootmem_low_pages or kmalloc/vmalloc. So, the kmalloc/vmalloc code is
removed.
Signed-off-by: Jeff Dike <jdike@linux.intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Restructure do_aio thanks to commments from Ulrich and Al.
Uli started this by seeing that UML's initialization of a struct iocb
initialized fields that it shouldn't.
Al followed up by adding the following cleanups:
eliminating a variable by just using an anonymous structure in
its place.
hoisting a duplicated line out of the switch.
simplifying the error checking at the end.
I added a severity to the printk.
Signed-off-by: Jeff Dike <jdike@linux.intel.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Ulrich Drepper <drepper@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
In 2.6.23-rc1, i386 fiddled its string support such that UML started getting
undefined references from modules. The UML asm/string.h was including the
i386 string.h, which defined __HAVE_ARCH_STR*, but the corresponding
implementations weren't being pulled in.
This is fixed by adding arch/i386/lib/string.h to the list of host
architecture files to be pulled in to UML.
A complication is that the libc exports file assumed that the generic strlen
and strstr weren't in use (i.e. __HAVE_ARCH_STR is defined), then they aren't
exported. This is untrue for strlen, which is exported in either case, so
this logic is not needed.
Signed-off-by: Jeff Dike <jdike@linux.intel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Added the MPC85xx PCI device IDs that we need for the quirks we have.
Also, fixed the MPC8567E, MPC8567 device IDs which had the wrong value.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Also add 8641/8641D device IDs as well.
All of which already exist or have been submitted to
The Linux PCI ID Repository at:
http://pci-ids.ucw.cz/
CC-to: pci-ids@ucw.cz
Signed-off-by: Jon Loeliger <jdl@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Added the P2P bridge present on the Arcadia base board and moved the VIA
Southbridge behind the bridge to reflect its actual position in the bus
organization. Added the RTC that's in the VIA Southbridge and expanded
the ranges array for the SOC node to allow proper address translation of
the RTC registers.
Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Setting the host bridge @8000 as primary. Also fixing a bug in
setting the USB interrupt numbers.
Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The interrupts of an E100 card inserted in PCI slot 4 may be on at bootup.
The resulting interrupt flood interacts with the 8259 cascade handler and
prevents proper boot up. There is a quirk for the E100 that will disable
the E100's interrupts but to use it, the 8259 cascade hookup must be
delayed until after the quirk has run. This patch delays the 8259 cascade
hookup by registering a device_initcall() which runs after the PCI quirk
for the E100.
Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
__INIT directive just before kernel_entry was ignored for most platforms.
This patch fixes it and get rid of this warning:
WARNING: vmlinux.o(.text+0x478): Section mismatch: reference to .init.text:start_kernel (between '_stext' and 'run_init_process')
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
We can make resources for platform_device_register_simple() "static
__initdata".
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Replaces the deprecated __attribute_used__ with __used. Also makes some
style adjustments to abide by the kernel coding conventions.
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: David Rientjes <rientjes@google.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
> WARNING: vmlinux.o(.text+0xbf20): Section mismatch: reference to
> .init.text:prom_free_prom_memory (between 'free_initmem' and 'copy_from_user_page')
prom_free_prom_memory() is called _before_ freeing init sections, so
it is false positive. __init_refok can be used for such cases.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Some of the code has been gradually transitioned to using the proper
struct request_queue, but there's lots left. So do a full sweet of
the kernel and get rid of this typedef and replace its uses with
the proper type.
Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
The current 85xxCDS restart code fails to reset the PCI bus which can
lead to odd behavior after the restart. This patch uses the VIA Super
Southbridge to perform a PCI reset which will reset the entire system.
NOTE: Since the VIA chip is behind a PCI-to-PCI bridge which can be
disabled with a switch setting, it may not be possible to perform the
PCI bus reset. In this case, the code defaults to the previous restart
mechanism.
Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The Freescale MPC8555CDS and MPC8548CDS reference hardware has a legacy
8259 interrupt controller pair contained within a VIA VT82C686B Southbridge
on the main carrier board. The processor complex plugs into the carrier
card using a PCI slot which limits the available interrupts to the
INTA-INTD PCI interrupts. The output of the 8259 cascade pair is routed
through a gate array and connected to the PCI INTA interrupt line.
The normal interrupt chaining hook (set_irq_chained_handler) does
not allow sharing of the chained interrupt which prevents the
use of PCI INTA by PCI devices. This patch allows the 8259 cascade
pair to share their interrupt line with PCI devices.
NOTE: The addition of the .end routine for the MPIC is not strictly
necessary for this patch. It's there so this code will run from within
the threaded interrupt context used by the Real Time patch.
Signed-off-by: Randy Vinson <rvinson@mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Some set of 85xx platforms have PCI-X controllers. The old arch/ppc
code setup these controllers and we haven't moved it over to arch/powerpc.
We use the PCI-X Capabilties to know if we are in PCI-X mode instead
of the Global Utilities PORDEVSR.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
For the Freescale PCIe PHBs Not all firmwares setup the virtual P2P
bridge registers properly. Make sure they get setup based on what
the struct pci_controller got from the device tree.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We need the ability to set P2P bridge registers to properly setup the virtual
P2P bridges that exist in PCIe controllers for some of the embedded setups.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add basic support for the PCIe PHB and enable the ULI bridge.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Make it so we do a runtime check to know if we need to write cfg_addr
as big or little endian. This is needed if we want to allow 86xx support
to co-exist in the same kernel as other 6xx PPCs.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
We don't use setup_indirect_pci_nomap in arch/powerpc and it appears
the users that needed it from arch/ppc are now using setup_indirect_pci.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The newer Arcadia boards for CDS have an FPGA that shows up on PCI
however isn't a real PCI device. Add a quirk to just ignore the
FPGA.
This is based on the following patch from Andy & York:
http://ozlabs.org/pipermail/linuxppc-dev/2007-February/032042.html
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
On the 85xx/86xx PCIe controllers if there is no device connected to the
PHB we will still allocate a pci_bus for downstream bus of the virtual
P2P bridge. However the resources allocated to the downstream bus are not
correct and so we just mimic the resources from the upstream pci_bus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Switch the 85xx platform over to using the FSL generic PCI code. This
gets ups PCIe support in addition to base PCI support.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Updated the 83xx & 85xx device tree PCI related compartible property.
Used the following compatible properties:
PCI "fsl,mpc8349-pci"
PCI "fsl,mpc8540-pci"
PCI-X: "fsl,mpc8540-pcix"
PCIe: "fsl,mpc8548-pcie"
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Add 8548 CDS PCI express controller node and PCI-X device node. The current
dts file is suitable for 8548 Rev 2.0 board with Arcadia 3.1.
This kind of board combination is the most popular.
Used the following compatible properties:
PCI "fsl,mpc8540-pci"
PCI-X: "fsl,mpc8540-pcix"
PCIe: "fsl,mpc8548-pcie"
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Use the PCI capabilities to determine if we are PCIe PHB. Also use
PPC_INDIRECT_TYPE_NO_PCIE_LINK since the Freescale PCIe controllers
will lock the system if they don't have link and you try to do a config
access to anything but the PHB.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
