From 6c06c88fa838fcc1b7e5380facd086f57fd9d1c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 4 Feb 2024 15:16:46 +0100 Subject: [PATCH 1/3] net: mdio: add 2.5g and 5g related PMA speed constants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add constants indicating 2.5g and 5g ability in the MMD PMA speed register. Signed-off-by: Marek Behún Signed-off-by: Heiner Kallweit Link: https://lore.kernel.org/r/98e15038-d96c-442f-93e4-410100d27866@gmail.com Signed-off-by: Jakub Kicinski --- include/uapi/linux/mdio.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/uapi/linux/mdio.h b/include/uapi/linux/mdio.h index d03863da180e..3c9097502403 100644 --- a/include/uapi/linux/mdio.h +++ b/include/uapi/linux/mdio.h @@ -138,6 +138,8 @@ #define MDIO_PMA_SPEED_1000 0x0010 /* 1000M capable */ #define MDIO_PMA_SPEED_100 0x0020 /* 100M capable */ #define MDIO_PMA_SPEED_10 0x0040 /* 10M capable */ +#define MDIO_PMA_SPEED_2_5G 0x2000 /* 2.5G capable */ +#define MDIO_PMA_SPEED_5G 0x4000 /* 5G capable */ #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */ #define MDIO_PCS_SPEED_2_5G 0x0040 /* 2.5G capable */ #define MDIO_PCS_SPEED_5G 0x0080 /* 5G capable */ From 2b9ec5dfb8255656ca731ab9d9bf59d94566d377 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Beh=C3=BAn?= Date: Sun, 4 Feb 2024 15:17:53 +0100 Subject: [PATCH 2/3] net: phy: realtek: use generic MDIO constants MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the ad-hoc MDIO constants used in the driver and use generic constants instead. Signed-off-by: Marek Behún Signed-off-by: Heiner Kallweit Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/732a70d6-4191-4aae-8862-3716b062aa9e@gmail.com Signed-off-by: Jakub Kicinski --- drivers/net/phy/realtek.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index 132784321e44..b5deccafdd9e 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -57,14 +57,6 @@ #define RTL8366RB_POWER_SAVE 0x15 #define RTL8366RB_POWER_SAVE_ON BIT(12) -#define RTL_SUPPORTS_5000FULL BIT(14) -#define RTL_SUPPORTS_2500FULL BIT(13) -#define RTL_SUPPORTS_10000FULL BIT(0) -#define RTL_ADV_2500FULL BIT(7) -#define RTL_LPADV_10000FULL BIT(11) -#define RTL_LPADV_5000FULL BIT(6) -#define RTL_LPADV_2500FULL BIT(5) - #define RTL9000A_GINMR 0x14 #define RTL9000A_GINMR_LINK_STATUS BIT(4) @@ -674,11 +666,11 @@ static int rtl822x_get_features(struct phy_device *phydev) return val; linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, - phydev->supported, val & RTL_SUPPORTS_2500FULL); + phydev->supported, val & MDIO_PMA_SPEED_2_5G); linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, - phydev->supported, val & RTL_SUPPORTS_5000FULL); + phydev->supported, val & MDIO_PMA_SPEED_5G); linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, - phydev->supported, val & RTL_SUPPORTS_10000FULL); + phydev->supported, val & MDIO_SPEED_10G); return genphy_read_abilities(phydev); } @@ -692,10 +684,11 @@ static int rtl822x_config_aneg(struct phy_device *phydev) if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) - adv2500 = RTL_ADV_2500FULL; + adv2500 = MDIO_AN_10GBT_CTRL_ADV2_5G; ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12, - RTL_ADV_2500FULL, adv2500); + MDIO_AN_10GBT_CTRL_ADV2_5G, + adv2500); if (ret < 0) return ret; } @@ -714,11 +707,14 @@ static int rtl822x_read_status(struct phy_device *phydev) return lpadv; linkmode_mod_bit(ETHTOOL_LINK_MODE_10000baseT_Full_BIT, - phydev->lp_advertising, lpadv & RTL_LPADV_10000FULL); + phydev->lp_advertising, + lpadv & MDIO_AN_10GBT_STAT_LP10G); linkmode_mod_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, - phydev->lp_advertising, lpadv & RTL_LPADV_5000FULL); + phydev->lp_advertising, + lpadv & MDIO_AN_10GBT_STAT_LP5G); linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, - phydev->lp_advertising, lpadv & RTL_LPADV_2500FULL); + phydev->lp_advertising, + lpadv & MDIO_AN_10GBT_STAT_LP2_5G); } ret = genphy_read_status(phydev); @@ -736,7 +732,7 @@ static bool rtlgen_supports_2_5gbps(struct phy_device *phydev) val = phy_read(phydev, 0x13); phy_write(phydev, RTL821x_PAGE_SELECT, 0); - return val >= 0 && val & RTL_SUPPORTS_2500FULL; + return val >= 0 && val & MDIO_PMA_SPEED_2_5G; } static int rtlgen_match_phy_device(struct phy_device *phydev) From db1bb7741ff29bf2cefcbc0ca567644e9ed1caa9 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Sun, 4 Feb 2024 15:18:50 +0100 Subject: [PATCH 3/3] net: phy: realtek: add 5Gbps support to rtl822x_config_aneg() RTL8126 as an evolution of RTL8125 supports 5Gbps. rtl822x_config_aneg() is used by the PHY driver for the integrated PHY, therefore add 5Gbps support to it. Signed-off-by: Heiner Kallweit Link: https://lore.kernel.org/r/5644ab50-e3e9-477c-96db-05cd5bdc2563@gmail.com Signed-off-by: Jakub Kicinski --- drivers/net/phy/realtek.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c index b5deccafdd9e..962df2b83070 100644 --- a/drivers/net/phy/realtek.c +++ b/drivers/net/phy/realtek.c @@ -680,15 +680,19 @@ static int rtl822x_config_aneg(struct phy_device *phydev) int ret = 0; if (phydev->autoneg == AUTONEG_ENABLE) { - u16 adv2500 = 0; + u16 adv = 0; if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising)) - adv2500 = MDIO_AN_10GBT_CTRL_ADV2_5G; + adv |= MDIO_AN_10GBT_CTRL_ADV2_5G; + if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT, + phydev->advertising)) + adv |= MDIO_AN_10GBT_CTRL_ADV5G; ret = phy_modify_paged_changed(phydev, 0xa5d, 0x12, - MDIO_AN_10GBT_CTRL_ADV2_5G, - adv2500); + MDIO_AN_10GBT_CTRL_ADV2_5G | + MDIO_AN_10GBT_CTRL_ADV5G, + adv); if (ret < 0) return ret; }