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Common clk support for S3C64XX
- add PLL for S3C64XX - add s3c64xx clock driver - update drivers to use CCF of s3c64xx -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.11 (GNU/Linux) iQIcBAABAgAGBQJSQK8VAAoJEA0Cl+kVi2xql9IP/2ZdMukndE/gxZpsHCwKSFgm pme2TxM4weN3q8c/749+r8AzwLl+RKbJdiw5DN4XDZ4cTdSSLkDkASUy0A0/r6Rg 147zoQSeI02HU9LgKzZP731x3wOOCAM+RdI3eT0idDSY14Z0cScNtp7tCU52BhEF OdZtQTDHdcnZuESUVGksRq2GM4V2KxlzBB/FNEtq28edEQa8gXmEdpfM7AkTtl1M e5JFmwY3xaL2qL/0A27trOyxsuyacx1K0GHWMaHeE6wpsVh3EzK2Bx/iHTcH1wre MIplDMUj18QEziuUgZ82M7sJ/VPYDugplZTI1tMKgln8ri5AA5Wtvn8e6intMntc f2VsZdOXlY0Uxz0SqGsLlxdMzi+rRy2HAlEuUKThQ8QMPxHB4uYKXjP1gZEskPwd BSIJ7vXXoPxIHlC7f2PIMPRyqcgLrPG8Y+/1Obcl5pQTyP8am1throJWPlyPKEuv yOqfuxfgZLXL1XJdcLDswgz+qRIPacbm7/1hM62wwGErjUo8m3wvmy88ZfR4Myo+ jj1avbsPthfInBl2/OMp9vGlZm6544SV7RtKU1/wuDNGPQba8+tr9FOiv7tJ2kRG xnLRcop9lu4qNqykeJkxGsOfHmTvYjG4N7TSrHunKJpN6fuVOQR93V1RSRAEX5e9 TvEuCjm3OJj4J1sARwke =bUyC -----END PGP SIGNATURE----- Merge tag 'samsung-clk-s3c64xx' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc From Kukjin Kim: Common clk support for S3C64XX - add PLL for S3C64XX - add s3c64xx clock driver - update drivers to use CCF of s3c64xx * tag 'samsung-clk-s3c64xx' of http://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: ARM: S3C64XX: Remove old clock management code ARM: S3C64XX: Migrate clock handling to Common Clock Framework usb: ohci-s3c2410.c: Use clk_prepare_enable/clk_disable_unprepare ARM: S3C64XX: Use clk_prepare_enable/clk_disable_unprepare in dma.c ARM: SAMSUNG: Add soc_is_s3c6400/s3c6410 macros Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
fca9b5ea3e
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@ -727,6 +727,7 @@ config ARCH_S3C64XX
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select ARM_VIC
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select CLKDEV_LOOKUP
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select CLKSRC_SAMSUNG_PWM
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select COMMON_CLK
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select CPU_V6
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select GENERIC_CLOCKEVENTS
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select GPIO_SAMSUNG
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@ -740,7 +741,6 @@ config ARCH_S3C64XX
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select S3C_DEV_NAND
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select S3C_GPIO_TRACK
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select SAMSUNG_ATAGS
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select SAMSUNG_CLKSRC
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select SAMSUNG_GPIOLIB_4BIT
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select SAMSUNG_WDT_RESET
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select USB_ARCH_HAS_OHCI
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@ -12,7 +12,7 @@ obj- :=
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# Core
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obj-y += common.o clock.o
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obj-y += common.o
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# Core support
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File diff suppressed because it is too large
Load diff
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@ -17,6 +17,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/clk-provider.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/serial_core.h>
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@ -38,7 +39,6 @@
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#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/clock.h>
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#include <plat/devs.h>
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#include <plat/pm.h>
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#include <plat/gpio-cfg.h>
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@ -50,6 +50,19 @@
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#include "common.h"
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/* External clock frequency */
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static unsigned long xtal_f = 12000000, xusbxti_f = 48000000;
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void __init s3c64xx_set_xtal_freq(unsigned long freq)
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{
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xtal_f = freq;
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}
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void __init s3c64xx_set_xusbxti_freq(unsigned long freq)
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{
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xusbxti_f = freq;
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}
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/* uart registration process */
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static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
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@ -67,7 +80,6 @@ static struct cpu_table cpu_ids[] __initdata = {
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.idcode = S3C6400_CPU_ID,
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.idmask = S3C64XX_CPU_MASK,
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.map_io = s3c6400_map_io,
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.init_clocks = s3c6400_init_clocks,
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.init_uarts = s3c64xx_init_uarts,
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.init = s3c6400_init,
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.name = name_s3c6400,
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@ -75,7 +87,6 @@ static struct cpu_table cpu_ids[] __initdata = {
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.idcode = S3C6410_CPU_ID,
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.idmask = S3C64XX_CPU_MASK,
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.map_io = s3c6410_map_io,
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.init_clocks = s3c6410_init_clocks,
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.init_uarts = s3c64xx_init_uarts,
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.init = s3c6410_init,
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.name = name_s3c6410,
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@ -213,8 +224,10 @@ void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
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{
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/*
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* FIXME: there is no better place to put this at the moment
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* (samsung_wdt_reset_init needs clocks)
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* (s3c64xx_clk_init needs ioremap and must happen before init_time
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* samsung_wdt_reset_init needs clocks)
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*/
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s3c64xx_clk_init(NULL, xtal_f, xusbxti_f, soc_is_s3c6400(), S3C_VA_SYS);
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samsung_wdt_reset_init(S3C_VA_WATCHDOG);
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printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
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@ -22,21 +22,21 @@
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void s3c64xx_init_irq(u32 vic0, u32 vic1);
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void s3c64xx_init_io(struct map_desc *mach_desc, int size);
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void s3c64xx_register_clocks(unsigned long xtal, unsigned armclk_limit);
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void s3c64xx_setup_clocks(void);
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void s3c64xx_restart(enum reboot_mode mode, const char *cmd);
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void s3c64xx_init_late(void);
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void s3c64xx_clk_init(struct device_node *np, unsigned long xtal_f,
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unsigned long xusbxti_f, bool is_s3c6400, void __iomem *reg_base);
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void s3c64xx_set_xtal_freq(unsigned long freq);
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void s3c64xx_set_xusbxti_freq(unsigned long freq);
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#ifdef CONFIG_CPU_S3C6400
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extern int s3c6400_init(void);
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extern void s3c6400_init_irq(void);
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extern void s3c6400_map_io(void);
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extern void s3c6400_init_clocks(int xtal);
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#else
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#define s3c6400_init_clocks NULL
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#define s3c6400_map_io NULL
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#define s3c6400_init NULL
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#endif
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@ -46,10 +46,8 @@ extern void s3c6400_init_clocks(int xtal);
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extern int s3c6410_init(void);
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extern void s3c6410_init_irq(void);
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extern void s3c6410_map_io(void);
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extern void s3c6410_init_clocks(int xtal);
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#else
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#define s3c6410_init_clocks NULL
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#define s3c6410_map_io NULL
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#define s3c6410_init NULL
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#endif
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@ -677,7 +677,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
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goto err_map;
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}
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clk_enable(dmac->clk);
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clk_prepare_enable(dmac->clk);
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dmac->regs = regs;
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dmac->chanbase = chbase;
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@ -711,7 +711,7 @@ static int s3c64xx_dma_init1(int chno, enum dma_ch chbase,
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return 0;
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err_clk:
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clk_disable(dmac->clk);
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clk_disable_unprepare(dmac->clk);
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clk_put(dmac->clk);
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err_map:
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iounmap(regs);
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@ -15,145 +15,21 @@
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#ifndef __PLAT_REGS_CLOCK_H
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#define __PLAT_REGS_CLOCK_H __FILE__
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/*
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* FIXME: Remove remaining definitions
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*/
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#define S3C_CLKREG(x) (S3C_VA_SYS + (x))
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#define S3C_APLL_LOCK S3C_CLKREG(0x00)
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#define S3C_MPLL_LOCK S3C_CLKREG(0x04)
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#define S3C_EPLL_LOCK S3C_CLKREG(0x08)
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#define S3C_APLL_CON S3C_CLKREG(0x0C)
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#define S3C_MPLL_CON S3C_CLKREG(0x10)
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#define S3C_EPLL_CON0 S3C_CLKREG(0x14)
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#define S3C_EPLL_CON1 S3C_CLKREG(0x18)
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#define S3C_CLK_SRC S3C_CLKREG(0x1C)
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#define S3C_CLK_DIV0 S3C_CLKREG(0x20)
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#define S3C_CLK_DIV1 S3C_CLKREG(0x24)
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#define S3C_CLK_DIV2 S3C_CLKREG(0x28)
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#define S3C_CLK_OUT S3C_CLKREG(0x2C)
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#define S3C_HCLK_GATE S3C_CLKREG(0x30)
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#define S3C_PCLK_GATE S3C_CLKREG(0x34)
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#define S3C_SCLK_GATE S3C_CLKREG(0x38)
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#define S3C_MEM0_GATE S3C_CLKREG(0x3C)
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#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
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#define S3C_MEM_SYS_CFG S3C_CLKREG(0x120)
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/* CLKDIV0 */
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#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
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#define S3C6400_CLKDIV0_PCLK_SHIFT (12)
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#define S3C6400_CLKDIV0_HCLK2_MASK (0x7 << 9)
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#define S3C6400_CLKDIV0_HCLK2_SHIFT (9)
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#define S3C6400_CLKDIV0_HCLK_MASK (0x1 << 8)
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#define S3C6400_CLKDIV0_HCLK_SHIFT (8)
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#define S3C6400_CLKDIV0_MPLL_MASK (0x1 << 4)
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#define S3C6400_CLKDIV0_MPLL_SHIFT (4)
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#define S3C6400_CLKDIV0_ARM_MASK (0x7 << 0)
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#define S3C6410_CLKDIV0_ARM_MASK (0xf << 0)
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#define S3C6400_CLKDIV0_ARM_SHIFT (0)
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/* HCLK GATE Registers */
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#define S3C_CLKCON_HCLK_3DSE (1<<31)
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#define S3C_CLKCON_HCLK_UHOST (1<<29)
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#define S3C_CLKCON_HCLK_SECUR (1<<28)
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#define S3C_CLKCON_HCLK_SDMA1 (1<<27)
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#define S3C_CLKCON_HCLK_SDMA0 (1<<26)
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#define S3C_CLKCON_HCLK_IROM (1<<25)
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#define S3C_CLKCON_HCLK_DDR1 (1<<24)
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#define S3C_CLKCON_HCLK_DDR0 (1<<23)
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#define S3C_CLKCON_HCLK_MEM1 (1<<22)
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#define S3C_CLKCON_HCLK_MEM0 (1<<21)
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#define S3C_CLKCON_HCLK_USB (1<<20)
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#define S3C_CLKCON_HCLK_HSMMC2 (1<<19)
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#define S3C_CLKCON_HCLK_HSMMC1 (1<<18)
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#define S3C_CLKCON_HCLK_HSMMC0 (1<<17)
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#define S3C_CLKCON_HCLK_MDP (1<<16)
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#define S3C_CLKCON_HCLK_DHOST (1<<15)
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#define S3C_CLKCON_HCLK_IHOST (1<<14)
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#define S3C_CLKCON_HCLK_DMA1 (1<<13)
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#define S3C_CLKCON_HCLK_DMA0 (1<<12)
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#define S3C_CLKCON_HCLK_JPEG (1<<11)
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#define S3C_CLKCON_HCLK_CAMIF (1<<10)
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#define S3C_CLKCON_HCLK_SCALER (1<<9)
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#define S3C_CLKCON_HCLK_2D (1<<8)
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#define S3C_CLKCON_HCLK_TV (1<<7)
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#define S3C_CLKCON_HCLK_POST0 (1<<5)
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#define S3C_CLKCON_HCLK_ROT (1<<4)
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#define S3C_CLKCON_HCLK_LCD (1<<3)
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#define S3C_CLKCON_HCLK_TZIC (1<<2)
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#define S3C_CLKCON_HCLK_INTC (1<<1)
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#define S3C_CLKCON_HCLK_MFC (1<<0)
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/* PCLK GATE Registers */
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#define S3C6410_CLKCON_PCLK_I2C1 (1<<27)
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#define S3C6410_CLKCON_PCLK_IIS2 (1<<26)
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#define S3C_CLKCON_PCLK_SKEY (1<<24)
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#define S3C_CLKCON_PCLK_CHIPID (1<<23)
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#define S3C_CLKCON_PCLK_SPI1 (1<<22)
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#define S3C_CLKCON_PCLK_SPI0 (1<<21)
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#define S3C_CLKCON_PCLK_HSIRX (1<<20)
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#define S3C_CLKCON_PCLK_HSITX (1<<19)
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#define S3C_CLKCON_PCLK_GPIO (1<<18)
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#define S3C_CLKCON_PCLK_IIC (1<<17)
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#define S3C_CLKCON_PCLK_IIS1 (1<<16)
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#define S3C_CLKCON_PCLK_IIS0 (1<<15)
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#define S3C_CLKCON_PCLK_AC97 (1<<14)
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#define S3C_CLKCON_PCLK_TZPC (1<<13)
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#define S3C_CLKCON_PCLK_TSADC (1<<12)
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#define S3C_CLKCON_PCLK_KEYPAD (1<<11)
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#define S3C_CLKCON_PCLK_IRDA (1<<10)
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#define S3C_CLKCON_PCLK_PCM1 (1<<9)
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#define S3C_CLKCON_PCLK_PCM0 (1<<8)
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#define S3C_CLKCON_PCLK_PWM (1<<7)
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#define S3C_CLKCON_PCLK_RTC (1<<6)
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#define S3C_CLKCON_PCLK_WDT (1<<5)
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#define S3C_CLKCON_PCLK_UART3 (1<<4)
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#define S3C_CLKCON_PCLK_UART2 (1<<3)
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#define S3C_CLKCON_PCLK_UART1 (1<<2)
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#define S3C_CLKCON_PCLK_UART0 (1<<1)
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#define S3C_CLKCON_PCLK_MFC (1<<0)
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/* SCLK GATE Registers */
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#define S3C_CLKCON_SCLK_UHOST (1<<30)
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#define S3C_CLKCON_SCLK_MMC2_48 (1<<29)
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#define S3C_CLKCON_SCLK_MMC1_48 (1<<28)
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#define S3C_CLKCON_SCLK_MMC0_48 (1<<27)
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#define S3C_CLKCON_SCLK_MMC2 (1<<26)
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#define S3C_CLKCON_SCLK_MMC1 (1<<25)
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#define S3C_CLKCON_SCLK_MMC0 (1<<24)
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#define S3C_CLKCON_SCLK_SPI1_48 (1<<23)
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#define S3C_CLKCON_SCLK_SPI0_48 (1<<22)
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#define S3C_CLKCON_SCLK_SPI1 (1<<21)
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#define S3C_CLKCON_SCLK_SPI0 (1<<20)
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#define S3C_CLKCON_SCLK_DAC27 (1<<19)
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#define S3C_CLKCON_SCLK_TV27 (1<<18)
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#define S3C_CLKCON_SCLK_SCALER27 (1<<17)
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#define S3C_CLKCON_SCLK_SCALER (1<<16)
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#define S3C_CLKCON_SCLK_LCD27 (1<<15)
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#define S3C_CLKCON_SCLK_LCD (1<<14)
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#define S3C6400_CLKCON_SCLK_POST1_27 (1<<13)
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#define S3C6410_CLKCON_FIMC (1<<13)
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#define S3C_CLKCON_SCLK_POST0_27 (1<<12)
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#define S3C6400_CLKCON_SCLK_POST1 (1<<11)
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#define S3C6410_CLKCON_SCLK_AUDIO2 (1<<11)
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#define S3C_CLKCON_SCLK_POST0 (1<<10)
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#define S3C_CLKCON_SCLK_AUDIO1 (1<<9)
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#define S3C_CLKCON_SCLK_AUDIO0 (1<<8)
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#define S3C_CLKCON_SCLK_SECUR (1<<7)
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#define S3C_CLKCON_SCLK_IRDA (1<<6)
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#define S3C_CLKCON_SCLK_UART (1<<5)
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#define S3C_CLKCON_SCLK_ONENAND (1<<4)
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#define S3C_CLKCON_SCLK_MFC (1<<3)
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#define S3C_CLKCON_SCLK_CAM (1<<2)
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#define S3C_CLKCON_SCLK_JPEG (1<<1)
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/* CLKSRC */
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#define S3C6400_CLKSRC_APLL_MOUT (1 << 0)
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#define S3C6400_CLKSRC_MPLL_MOUT (1 << 1)
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#define S3C6400_CLKSRC_EPLL_MOUT (1 << 2)
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#define S3C6400_CLKSRC_APLL_MOUT_SHIFT (0)
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#define S3C6400_CLKSRC_MPLL_MOUT_SHIFT (1)
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#define S3C6400_CLKSRC_EPLL_MOUT_SHIFT (2)
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#define S3C6400_CLKSRC_MFC (1 << 4)
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/* MEM_SYS_CFG */
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#define MEM_SYS_CFG_INDEP_CF 0x4000
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@ -207,7 +207,7 @@ static struct platform_device *anw6410_devices[] __initdata = {
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static void __init anw6410_map_io(void)
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{
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s3c64xx_init_io(anw6410_iodesc, ARRAY_SIZE(anw6410_iodesc));
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s3c24xx_init_clocks(12000000);
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s3c64xx_set_xtal_freq(12000000);
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s3c24xx_init_uarts(anw6410_uartcfgs, ARRAY_SIZE(anw6410_uartcfgs));
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samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
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|
|
@ -743,7 +743,7 @@ static struct s3c2410_platform_i2c i2c1_pdata = {
|
|||
static void __init crag6410_map_io(void)
|
||||
{
|
||||
s3c64xx_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c64xx_set_xtal_freq(12000000);
|
||||
s3c24xx_init_uarts(crag6410_uartcfgs, ARRAY_SIZE(crag6410_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
|
||||
|
|
|
|||
|
|
@ -247,7 +247,7 @@ static struct platform_device *hmt_devices[] __initdata = {
|
|||
static void __init hmt_map_io(void)
|
||||
{
|
||||
s3c64xx_init_io(hmt_iodesc, ARRAY_SIZE(hmt_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c64xx_set_xtal_freq(12000000);
|
||||
s3c24xx_init_uarts(hmt_uartcfgs, ARRAY_SIZE(hmt_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -231,7 +231,7 @@ static void __init mini6410_map_io(void)
|
|||
u32 tmp;
|
||||
|
||||
s3c64xx_init_io(NULL, 0);
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c64xx_set_xtal_freq(12000000);
|
||||
s3c24xx_init_uarts(mini6410_uartcfgs, ARRAY_SIZE(mini6410_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
|
||||
|
|
|
|||
|
|
@ -86,7 +86,7 @@ static struct map_desc ncp_iodesc[] __initdata = {};
|
|||
static void __init ncp_map_io(void)
|
||||
{
|
||||
s3c64xx_init_io(ncp_iodesc, ARRAY_SIZE(ncp_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c64xx_set_xtal_freq(12000000);
|
||||
s3c24xx_init_uarts(ncp_uartcfgs, ARRAY_SIZE(ncp_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -337,13 +337,6 @@ static int __init smartq_usb_host_init(void)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int __init smartq_usb_otg_init(void)
|
||||
{
|
||||
clk_xusbxti.rate = 12000000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int __init smartq_wifi_init(void)
|
||||
{
|
||||
int ret;
|
||||
|
|
@ -377,7 +370,8 @@ static struct map_desc smartq_iodesc[] __initdata = {};
|
|||
void __init smartq_map_io(void)
|
||||
{
|
||||
s3c64xx_init_io(smartq_iodesc, ARRAY_SIZE(smartq_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c64xx_set_xtal_freq(12000000);
|
||||
s3c64xx_set_xusbxti_freq(12000000);
|
||||
s3c24xx_init_uarts(smartq_uartcfgs, ARRAY_SIZE(smartq_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
|
||||
|
|
@ -399,7 +393,6 @@ void __init smartq_machine_init(void)
|
|||
WARN_ON(smartq_lcd_setup_gpio());
|
||||
WARN_ON(smartq_power_off_init());
|
||||
WARN_ON(smartq_usb_host_init());
|
||||
WARN_ON(smartq_usb_otg_init());
|
||||
WARN_ON(smartq_wifi_init());
|
||||
|
||||
platform_add_devices(smartq_devices, ARRAY_SIZE(smartq_devices));
|
||||
|
|
|
|||
|
|
@ -65,7 +65,7 @@ static struct map_desc smdk6400_iodesc[] = {};
|
|||
static void __init smdk6400_map_io(void)
|
||||
{
|
||||
s3c64xx_init_io(smdk6400_iodesc, ARRAY_SIZE(smdk6400_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c64xx_set_xtal_freq(12000000);
|
||||
s3c24xx_init_uarts(smdk6400_uartcfgs, ARRAY_SIZE(smdk6400_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -634,7 +634,7 @@ static void __init smdk6410_map_io(void)
|
|||
u32 tmp;
|
||||
|
||||
s3c64xx_init_io(smdk6410_iodesc, ARRAY_SIZE(smdk6410_iodesc));
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c64xx_set_xtal_freq(12000000);
|
||||
s3c24xx_init_uarts(smdk6410_uartcfgs, ARRAY_SIZE(smdk6410_uartcfgs));
|
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
|
||||
|
||||
|
|
|
|||
|
|
@ -194,29 +194,8 @@ void s3c_pm_debug_smdkled(u32 set, u32 clear)
|
|||
#endif
|
||||
|
||||
static struct sleep_save core_save[] = {
|
||||
SAVE_ITEM(S3C_APLL_LOCK),
|
||||
SAVE_ITEM(S3C_MPLL_LOCK),
|
||||
SAVE_ITEM(S3C_EPLL_LOCK),
|
||||
SAVE_ITEM(S3C_CLK_SRC),
|
||||
SAVE_ITEM(S3C_CLK_DIV0),
|
||||
SAVE_ITEM(S3C_CLK_DIV1),
|
||||
SAVE_ITEM(S3C_CLK_DIV2),
|
||||
SAVE_ITEM(S3C_CLK_OUT),
|
||||
SAVE_ITEM(S3C_HCLK_GATE),
|
||||
SAVE_ITEM(S3C_PCLK_GATE),
|
||||
SAVE_ITEM(S3C_SCLK_GATE),
|
||||
SAVE_ITEM(S3C_MEM0_GATE),
|
||||
|
||||
SAVE_ITEM(S3C_EPLL_CON1),
|
||||
SAVE_ITEM(S3C_EPLL_CON0),
|
||||
|
||||
SAVE_ITEM(S3C64XX_MEM0DRVCON),
|
||||
SAVE_ITEM(S3C64XX_MEM1DRVCON),
|
||||
|
||||
#ifndef CONFIG_CPU_FREQ
|
||||
SAVE_ITEM(S3C_APLL_CON),
|
||||
SAVE_ITEM(S3C_MPLL_CON),
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct sleep_save misc_save[] = {
|
||||
|
|
|
|||
|
|
@ -58,12 +58,6 @@ void __init s3c6400_map_io(void)
|
|||
s3c64xx_onenand1_setname("s3c6400-onenand");
|
||||
}
|
||||
|
||||
void __init s3c6400_init_clocks(int xtal)
|
||||
{
|
||||
s3c64xx_register_clocks(xtal, S3C6400_CLKDIV0_ARM_MASK);
|
||||
s3c64xx_setup_clocks();
|
||||
}
|
||||
|
||||
void __init s3c6400_init_irq(void)
|
||||
{
|
||||
/* VIC0 does not have IRQS 5..7,
|
||||
|
|
|
|||
|
|
@ -62,13 +62,6 @@ void __init s3c6410_map_io(void)
|
|||
s3c_cfcon_setname("s3c64xx-pata");
|
||||
}
|
||||
|
||||
void __init s3c6410_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initialising clocks\n", __func__);
|
||||
s3c64xx_register_clocks(xtal, S3C6410_CLKDIV0_ARM_MASK);
|
||||
s3c64xx_setup_clocks();
|
||||
}
|
||||
|
||||
void __init s3c6410_init_irq(void)
|
||||
{
|
||||
/* VIC0 is missing IRQ7, VIC1 is fully populated. */
|
||||
|
|
|
|||
|
|
@ -87,8 +87,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
|
|||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
|
||||
# define soc_is_s3c6400() is_samsung_s3c6400()
|
||||
# define soc_is_s3c6410() is_samsung_s3c6410()
|
||||
# define soc_is_s3c64xx() (is_samsung_s3c6400() || is_samsung_s3c6410())
|
||||
#else
|
||||
# define soc_is_s3c6400() 0
|
||||
# define soc_is_s3c6410() 0
|
||||
# define soc_is_s3c64xx() 0
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -8,6 +8,4 @@ obj-$(CONFIG_SOC_EXYNOS5250) += clk-exynos5250.o
|
|||
obj-$(CONFIG_SOC_EXYNOS5420) += clk-exynos5420.o
|
||||
obj-$(CONFIG_SOC_EXYNOS5440) += clk-exynos5440.o
|
||||
obj-$(CONFIG_ARCH_EXYNOS) += clk-exynos-audss.o
|
||||
ifdef CONFIG_COMMON_CLK
|
||||
obj-$(CONFIG_ARCH_S3C64XX) += clk-s3c64xx.o
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -47,10 +47,10 @@ static void s3c2410_start_hc(struct platform_device *dev, struct usb_hcd *hcd)
|
|||
|
||||
dev_dbg(&dev->dev, "s3c2410_start_hc:\n");
|
||||
|
||||
clk_enable(usb_clk);
|
||||
clk_prepare_enable(usb_clk);
|
||||
mdelay(2); /* let the bus clock stabilise */
|
||||
|
||||
clk_enable(clk);
|
||||
clk_prepare_enable(clk);
|
||||
|
||||
if (info != NULL) {
|
||||
info->hcd = hcd;
|
||||
|
|
@ -75,8 +75,8 @@ static void s3c2410_stop_hc(struct platform_device *dev)
|
|||
(info->enable_oc)(info, 0);
|
||||
}
|
||||
|
||||
clk_disable(clk);
|
||||
clk_disable(usb_clk);
|
||||
clk_disable_unprepare(clk);
|
||||
clk_disable_unprepare(usb_clk);
|
||||
}
|
||||
|
||||
/* ohci_s3c2410_hub_status_data
|
||||
|
|
|
|||
Loading…
Reference in a new issue