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dmaengine: dw-axi-dmac: support parallel memory <--> peripheral transfers

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Added support for multiple DMA_MEM_TO_DEV, DMA_DEV_TO_MEM transfers in
parallel. This is required for peripherals using DMA for transmit and
receive operations at the same time. APB slot number needs to be
programmed in channel hardware handshaking interface

Signed-off-by: Pandith N <pandith.n@intel.com>
Tested-by: Pan Kris <kris.pan@intel.com>
Link: https://lore.kernel.org/r/20210802055454.15192-3-pandith.n@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Pandith N 2021-08-02 11:24:53 +05:30 committed by Vinod Koul
parent 32286e2793
commit f95f3b5351
2 changed files with 6 additions and 0 deletions
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4
drivers/dma/dw-axi-dmac/dw-axi-dmac-platform.c
View file

@ -363,12 +363,16 @@ static void axi_chan_block_xfer_start(struct axi_dma_chan *chan,
DWAXIDMAC_TT_FC_MEM_TO_PER_DST : DWAXIDMAC_TT_FC_MEM_TO_PER_DST :
DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC) DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC)
<< CH_CFG_H_TT_FC_POS; << CH_CFG_H_TT_FC_POS;
if (chan->chip->apb_regs)
reg |= (chan->id << CH_CFG_H_DST_PER_POS);
break; break;
case DMA_DEV_TO_MEM: case DMA_DEV_TO_MEM:
reg |= (chan->config.device_fc ? reg |= (chan->config.device_fc ?
DWAXIDMAC_TT_FC_PER_TO_MEM_SRC : DWAXIDMAC_TT_FC_PER_TO_MEM_SRC :
DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC) DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC)
<< CH_CFG_H_TT_FC_POS; << CH_CFG_H_TT_FC_POS;
if (chan->chip->apb_regs)
reg |= (chan->id << CH_CFG_H_SRC_PER_POS);
break; break;
default: default:
break; break;

2
drivers/dma/dw-axi-dmac/dw-axi-dmac.h
View file

@ -258,6 +258,8 @@ enum {
/* CH_CFG_H */ /* CH_CFG_H */
#define CH_CFG_H_PRIORITY_POS 17 #define CH_CFG_H_PRIORITY_POS 17
#define CH_CFG_H_DST_PER_POS 12
#define CH_CFG_H_SRC_PER_POS 7
#define CH_CFG_H_HS_SEL_DST_POS 4 #define CH_CFG_H_HS_SEL_DST_POS 4
#define CH_CFG_H_HS_SEL_SRC_POS 3 #define CH_CFG_H_HS_SEL_SRC_POS 3
enum { enum {