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drm/amd/display: Fix FRL assertion on boot

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[why]
Make sure to ungate the clocks on boot
so programming sequence is done successfully.

[how]
Move the ungate logic after bios init.

Reviewed-by: Xi (Alex) Liu <xi.liu@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Signed-off-by: Sung Joon Kim <sungkim@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sung Joon Kim 2023-10-16 15:23:16 -04:00 committed by Alex Deucher
parent 566f648c4e
commit f896cd2686
1 changed files with 5 additions and 4 deletions
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9
drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
View file

@ -138,16 +138,17 @@ void dcn35_init_hw(struct dc *dc)
if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0x3F000000);
REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0x1f7c3fcf);
//dcn35_set_dmu_fgcg(hws, dc->debug.enable_fine_grain_clock_gating.bits.dmu);
if (!dcb->funcs->is_accelerated_mode(dcb)) {
/*this calls into dmubfw to do the init*/
hws->funcs.bios_golden_init(dc);
}
REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0x3F000000);
REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0x1f7c3fcf);
// Initialize the dccg
if (res_pool->dccg->funcs->dccg_init)
res_pool->dccg->funcs->dccg_init(res_pool->dccg);