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perf list: Update event description for IBM z10 to latest level
Update IBM z10 event counter description to the latest level
as described in the documents
1. SA23-2260-07:
"The Load-Program-Parameter and the CPU-Measurement Facilities."
released on May, 2022
for the following counter sets:
* Basic counter set
* Problem counter set
* Crypto counter set
2. SA23-2261-07:
"The CPU-Measurement Facility Extended Counters Definition
for z10, z196/z114, zEC12/zBC12, z13/z13s, z14, z15 and z16"
released on April 29, 2022
for the following counter sets:
* Extended counter set
* MT-Diagnostic counter set
Signed-off-by: Thomas Richter <tmricht@linux.ibm.com>
Acked-by: Sumanth Korikkar <sumanthk@linux.ibm.com>
Acked-by: Ian Rogers <irogers@google.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Link: https://lore.kernel.org/r/20220531092706.1931503-2-tmricht@linux.ibm.com
Cc: acme@kernel.org
Cc: gor@linux.ibm.com
Cc: hca@linux.ibm.com
Cc: svens@linux.ibm.com
Cc: linux-kernel@vger.kernel.org
Cc: linux-perf-users@vger.kernel.org
This commit is contained in:
Thomas Richter
Arnaldo Carvalho de Melo
parent
7f76b31130
commit
f71a261acd
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@ -3,84 +3,84 @@
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"Unit": "CPU-M-CF",
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"EventCode": "0",
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"EventName": "CPU_CYCLES",
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"BriefDescription": "CPU Cycles",
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"PublicDescription": "Cycle Count"
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"BriefDescription": "Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "1",
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"EventName": "INSTRUCTIONS",
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"BriefDescription": "Instructions",
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"PublicDescription": "Instruction Count"
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"BriefDescription": "Instruction Count",
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"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "2",
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"EventName": "L1I_DIR_WRITES",
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"BriefDescription": "L1I Directory Writes",
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"PublicDescription": "Level-1 I-Cache Directory Write Count"
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"BriefDescription": "Level-1 I-Cache Directory Write Count",
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"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "3",
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"EventName": "L1I_PENALTY_CYCLES",
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"BriefDescription": "L1I Penalty Cycles",
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"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
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"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "4",
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"EventName": "L1D_DIR_WRITES",
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"BriefDescription": "L1D Directory Writes",
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"PublicDescription": "Level-1 D-Cache Directory Write Count"
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"BriefDescription": "Level-1 D-Cache Directory Write Count",
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"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "5",
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"EventName": "L1D_PENALTY_CYCLES",
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"BriefDescription": "L1D Penalty Cycles",
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"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
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"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
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"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "32",
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"EventName": "PROBLEM_STATE_CPU_CYCLES",
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"BriefDescription": "Problem-State CPU Cycles",
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"PublicDescription": "Problem-State Cycle Count"
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"BriefDescription": "Problem-State Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "33",
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"EventName": "PROBLEM_STATE_INSTRUCTIONS",
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"BriefDescription": "Problem-State Instructions",
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"PublicDescription": "Problem-State Instruction Count"
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"BriefDescription": "Problem-State Instruction Count",
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"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "34",
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"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
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"BriefDescription": "Problem-State L1I Directory Writes",
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"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
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"BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count",
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"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "35",
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"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
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"BriefDescription": "Problem-State L1I Penalty Cycles",
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"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
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"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
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"PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "36",
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"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
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"BriefDescription": "Problem-State L1D Directory Writes",
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"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
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"BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count",
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"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "37",
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"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
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"BriefDescription": "Problem-State L1D Penalty Cycles",
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"PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
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"BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count",
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"PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state."
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}
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]
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@ -3,112 +3,112 @@
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"Unit": "CPU-M-CF",
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"EventCode": "64",
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"EventName": "PRNG_FUNCTIONS",
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"BriefDescription": "PRNG Functions",
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"PublicDescription": "Total number of the PRNG functions issued by the CPU"
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"BriefDescription": "PRNG Function Count",
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"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "65",
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"EventName": "PRNG_CYCLES",
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"BriefDescription": "PRNG Cycles",
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"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing PRNG functions issued by the CPU"
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"BriefDescription": "PRNG Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES/SHA coprocessor is busy performing the pseudorandom- number-generation functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "66",
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"EventName": "PRNG_BLOCKED_FUNCTIONS",
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"BriefDescription": "PRNG Blocked Functions",
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"PublicDescription": "Total number of the PRNG functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"BriefDescription": "PRNG Blocked Function Count",
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"PublicDescription": "This counter counts the total number of the pseudorandom-number-generation functions that are issued by the CPU and are blocked because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "67",
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"EventName": "PRNG_BLOCKED_CYCLES",
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"BriefDescription": "PRNG Blocked Cycles",
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"PublicDescription": "Total number of CPU cycles blocked for the PRNG functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"BriefDescription": "PRNG Blocked Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the pseudorandom-number-generation functions issued by the CPU because the DEA/AES/SHA coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "68",
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"EventName": "SHA_FUNCTIONS",
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"BriefDescription": "SHA Functions",
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"PublicDescription": "Total number of SHA functions issued by the CPU"
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"BriefDescription": "SHA Function Count",
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"PublicDescription": "This counter counts the total number of the SHA functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "69",
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"EventName": "SHA_CYCLES",
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"BriefDescription": "SHA Cycles",
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"PublicDescription": "Total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU"
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"BriefDescription": "SHA Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the SHA coprocessor is busy performing the SHA functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "70",
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"EventName": "SHA_BLOCKED_FUNCTIONS",
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"BriefDescription": "SHA Blocked Functions",
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"PublicDescription": "Total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU"
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"BriefDescription": "SHA Blocked Function Count",
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"PublicDescription": "This counter counts the total number of the SHA functions that are issued by the CPU and are blocked because the SHA coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "71",
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"EventName": "SHA_BLOCKED_CYCLES",
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"BriefDescription": "SHA Bloced Cycles",
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"PublicDescription": "Total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU"
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"BriefDescription": "SHA Blocked Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the SHA functions issued by the CPU because the SHA coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "72",
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"EventName": "DEA_FUNCTIONS",
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"BriefDescription": "DEA Functions",
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"PublicDescription": "Total number of the DEA functions issued by the CPU"
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"BriefDescription": "DEA Function Count",
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"PublicDescription": "This counter counts the total number of the DEA functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "73",
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"EventName": "DEA_CYCLES",
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"BriefDescription": "DEA Cycles",
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"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU"
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"BriefDescription": "DEA Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the DEA functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "74",
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"EventName": "DEA_BLOCKED_FUNCTIONS",
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"BriefDescription": "DEA Blocked Functions",
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"PublicDescription": "Total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"BriefDescription": "DEA Blocked Function Count",
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"PublicDescription": "This counter counts the total number of the DEA functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "75",
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"EventName": "DEA_BLOCKED_CYCLES",
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"BriefDescription": "DEA Blocked Cycles",
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"PublicDescription": "Total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"BriefDescription": "DEA Blocked Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the DEA functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "76",
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"EventName": "AES_FUNCTIONS",
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"BriefDescription": "AES Functions",
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"PublicDescription": "Total number of AES functions issued by the CPU"
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"BriefDescription": "AES Function Count",
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"PublicDescription": "This counter counts the total number of the AES functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "77",
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"EventName": "AES_CYCLES",
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"BriefDescription": "AES Cycles",
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"PublicDescription": "Total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU"
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"BriefDescription": "AES Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles when the DEA/AES coprocessor is busy performing the AES functions issued by the CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "78",
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"EventName": "AES_BLOCKED_FUNCTIONS",
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"BriefDescription": "AES Blocked Functions",
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"PublicDescription": "Total number of AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"BriefDescription": "AES Blocked Function Count",
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"PublicDescription": "This counter counts the total number of the AES functions that are issued by the CPU and are blocked because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "79",
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"EventName": "AES_BLOCKED_CYCLES",
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"BriefDescription": "AES Blocked Cycles",
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"PublicDescription": "Total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU"
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"BriefDescription": "AES Blocked Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles blocked for the AES functions issued by the CPU because the DEA/AES coprocessor is busy performing a function issued by another CPU."
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}
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]
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@ -4,125 +4,125 @@
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"EventCode": "128",
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"EventName": "L1I_L2_SOURCED_WRITES",
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"BriefDescription": "L1I L2 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 I-Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache"
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"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "129",
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"EventName": "L1D_L2_SOURCED_WRITES",
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"BriefDescription": "L1D L2 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache"
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "130",
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"EventName": "L1I_L3_LOCAL_WRITES",
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"BriefDescription": "L1I L3 Local Writes",
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"PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)"
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"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "131",
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"EventName": "L1D_L3_LOCAL_WRITES",
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"BriefDescription": "L1D L3 Local Writes",
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"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installtion cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)"
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "132",
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"EventName": "L1I_L3_REMOTE_WRITES",
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"BriefDescription": "L1I L3 Remote Writes",
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"PublicDescription": "A directory write to the Level-1 I-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)"
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"PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "133",
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"EventName": "L1D_L3_REMOTE_WRITES",
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"BriefDescription": "L1D L3 Remote Writes",
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"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)"
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "134",
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"EventName": "L1D_LMEM_SOURCED_WRITES",
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"BriefDescription": "L1D Local Memory Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 D-Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)"
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"PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "135",
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"EventName": "L1I_LMEM_SOURCED_WRITES",
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"BriefDescription": "L1I Local Memory Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 I-Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)"
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"PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "136",
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"EventName": "L1D_RO_EXCL_WRITES",
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"BriefDescription": "L1D Read-only Exclusive Writes",
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"PublicDescription": "A directory write to the Level-1 D-Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line"
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"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "137",
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"EventName": "L1I_CACHELINE_INVALIDATES",
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"BriefDescription": "L1I Cacheline Invalidates",
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"PublicDescription": "A cache line in the Level-1 I-Cache has been invalidated by a store on the same CPU as the Level-1 I-Cache"
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"PublicDescription": "A cache line in the Level-1 Instruction Cache has been invalidated by a store on the same CPU as the Level-1 Instruction Cache."
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},
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{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "138",
|
||||
"EventName": "ITLB1_WRITES",
|
||||
"BriefDescription": "ITLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer"
|
||||
"PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "139",
|
||||
"EventName": "DTLB1_WRITES",
|
||||
"BriefDescription": "DTLB1 Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer"
|
||||
"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "140",
|
||||
"EventName": "TLB2_PTE_WRITES",
|
||||
"BriefDescription": "TLB2 PTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays"
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "141",
|
||||
"EventName": "TLB2_CRSTE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays"
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "142",
|
||||
"EventName": "TLB2_CRSTE_HPAGE_WRITES",
|
||||
"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation"
|
||||
"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "145",
|
||||
"EventName": "ITLB1_MISSES",
|
||||
"BriefDescription": "ITLB1 Misses",
|
||||
"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress"
|
||||
"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "146",
|
||||
"EventName": "DTLB1_MISSES",
|
||||
"BriefDescription": "DTLB1 Misses",
|
||||
"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress"
|
||||
"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress."
|
||||
},
|
||||
{
|
||||
"Unit": "CPU-M-CF",
|
||||
"EventCode": "147",
|
||||
"EventName": "L2C_STORES_SENT",
|
||||
"BriefDescription": "L2C Stores Sent",
|
||||
"PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache"
|
||||
"PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache."
|
||||
}
|
||||
]
|
||||
|
|
|
|||
Loading…
Reference in a new issue