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https://github.com/torvalds/linux
synced 2024-09-22 03:55:39 +00:00
dmaengine: i.MX: Add support for interleaved transfers.
i.MX2 and i.MX1 chips have the possibility to do interleaved transfers with two constraints: - Only one chunk can be used (i.e. only 2D transfers are allowed). - Only 2 interleaved configurations can be applied at the same time for all channels. Since this patch adds a new resource 'slots_2d' which is shared by all the DMA channels and to avoid disgustin locking BUGs, the 'lock' member has been moved to the global 'imxdma_engine' structure. Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
This commit is contained in:
Javier Martin
Vinod Koul
parent
f9b283a6e4
commit
f606ab897b
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@ -36,6 +36,10 @@
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#define IMXDMA_MAX_CHAN_DESCRIPTORS 16
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#define IMX_DMA_CHANNELS 16
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#define IMX_DMA_2D_SLOTS 2
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#define IMX_DMA_2D_SLOT_A 0
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#define IMX_DMA_2D_SLOT_B 1
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#define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
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#define IMX_DMA_MEMSIZE_32 (0 << 4)
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#define IMX_DMA_MEMSIZE_8 (1 << 4)
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@ -111,6 +115,13 @@ enum imxdma_prep_type {
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IMXDMA_DESC_CYCLIC,
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};
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struct imx_dma_2d_config {
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u16 xsr;
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u16 ysr;
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u16 wsr;
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int count;
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};
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struct imxdma_desc {
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struct list_head node;
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struct dma_async_tx_descriptor desc;
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@ -147,13 +158,14 @@ struct imxdma_channel {
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dma_addr_t per_address;
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u32 watermark_level;
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struct dma_chan chan;
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spinlock_t lock;
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struct dma_async_tx_descriptor desc;
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enum dma_status status;
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int dma_request;
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struct scatterlist *sg_list;
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u32 ccr_from_device;
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u32 ccr_to_device;
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bool enabled_2d;
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int slot_2d;
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};
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struct imxdma_engine {
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@ -162,6 +174,8 @@ struct imxdma_engine {
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struct dma_device dma_device;
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void __iomem *base;
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struct clk *dma_clk;
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spinlock_t lock;
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struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
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struct imxdma_channel channel[IMX_DMA_CHANNELS];
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};
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@ -361,16 +375,16 @@ static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
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int chno = imxdmac->channel;
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struct imxdma_desc *desc;
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spin_lock(&imxdmac->lock);
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spin_lock(&imxdma->lock);
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if (list_empty(&imxdmac->ld_active)) {
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spin_unlock(&imxdmac->lock);
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spin_unlock(&imxdma->lock);
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goto out;
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}
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desc = list_first_entry(&imxdmac->ld_active,
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struct imxdma_desc,
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node);
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spin_unlock(&imxdmac->lock);
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spin_unlock(&imxdma->lock);
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if (desc->sg) {
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u32 tmp;
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@ -442,9 +456,53 @@ static int imxdma_xfer_desc(struct imxdma_desc *d)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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unsigned long flags;
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int slot = -1;
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int i;
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/* Configure and enable */
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switch (d->type) {
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case IMXDMA_DESC_INTERLEAVED:
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/* Try to get a free 2D slot */
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spin_lock_irqsave(&imxdma->lock, flags);
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for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
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if ((imxdma->slots_2d[i].count > 0) &&
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((imxdma->slots_2d[i].xsr != d->x) ||
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(imxdma->slots_2d[i].ysr != d->y) ||
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(imxdma->slots_2d[i].wsr != d->w)))
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continue;
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slot = i;
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break;
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}
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if (slot < 0)
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return -EBUSY;
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imxdma->slots_2d[slot].xsr = d->x;
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imxdma->slots_2d[slot].ysr = d->y;
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imxdma->slots_2d[slot].wsr = d->w;
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imxdma->slots_2d[slot].count++;
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imxdmac->slot_2d = slot;
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imxdmac->enabled_2d = true;
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spin_unlock_irqrestore(&imxdma->lock, flags);
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if (slot == IMX_DMA_2D_SLOT_A) {
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d->config_mem &= ~CCR_MSEL_B;
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d->config_port &= ~CCR_MSEL_B;
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imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
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imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
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imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
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} else {
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d->config_mem |= CCR_MSEL_B;
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d->config_port |= CCR_MSEL_B;
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imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
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imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
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imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
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}
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/*
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* We fall-through here intentionally, since a 2D transfer is
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* similar to MEMCPY just adding the 2D slot configuration.
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*/
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case IMXDMA_DESC_MEMCPY:
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imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
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imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
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@ -503,7 +561,7 @@ static void imxdma_tasklet(unsigned long data)
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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struct imxdma_desc *desc;
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spin_lock(&imxdmac->lock);
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spin_lock(&imxdma->lock);
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if (list_empty(&imxdmac->ld_active)) {
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/* Someone might have called terminate all */
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@ -520,6 +578,12 @@ static void imxdma_tasklet(unsigned long data)
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if (imxdma_chan_is_doing_cyclic(imxdmac))
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goto out;
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/* Free 2D slot if it was an interleaved transfer */
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if (imxdmac->enabled_2d) {
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imxdma->slots_2d[imxdmac->slot_2d].count--;
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imxdmac->enabled_2d = false;
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}
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list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
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if (!list_empty(&imxdmac->ld_queue)) {
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@ -531,7 +595,7 @@ static void imxdma_tasklet(unsigned long data)
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__func__, imxdmac->channel);
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}
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out:
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spin_unlock(&imxdmac->lock);
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spin_unlock(&imxdma->lock);
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}
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static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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@ -547,10 +611,10 @@ static int imxdma_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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case DMA_TERMINATE_ALL:
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imxdma_disable_hw(imxdmac);
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spin_lock_irqsave(&imxdmac->lock, flags);
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spin_lock_irqsave(&imxdma->lock, flags);
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list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
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list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
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spin_unlock_irqrestore(&imxdmac->lock, flags);
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spin_unlock_irqrestore(&imxdma->lock, flags);
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return 0;
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case DMA_SLAVE_CONFIG:
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if (dmaengine_cfg->direction == DMA_DEV_TO_MEM) {
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@ -610,12 +674,13 @@ static enum dma_status imxdma_tx_status(struct dma_chan *chan,
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static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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dma_cookie_t cookie;
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unsigned long flags;
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spin_lock_irqsave(&imxdmac->lock, flags);
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spin_lock_irqsave(&imxdma->lock, flags);
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cookie = dma_cookie_assign(tx);
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spin_unlock_irqrestore(&imxdmac->lock, flags);
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spin_unlock_irqrestore(&imxdma->lock, flags);
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return cookie;
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}
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@ -654,16 +719,17 @@ static int imxdma_alloc_chan_resources(struct dma_chan *chan)
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static void imxdma_free_chan_resources(struct dma_chan *chan)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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struct imxdma_desc *desc, *_desc;
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unsigned long flags;
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spin_lock_irqsave(&imxdmac->lock, flags);
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spin_lock_irqsave(&imxdma->lock, flags);
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imxdma_disable_hw(imxdmac);
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list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
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list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
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spin_unlock_irqrestore(&imxdmac->lock, flags);
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spin_unlock_irqrestore(&imxdma->lock, flags);
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list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
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kfree(desc);
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@ -818,6 +884,49 @@ static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
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return &desc->desc;
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}
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static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
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struct dma_chan *chan, struct dma_interleaved_template *xt,
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unsigned long flags)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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struct imxdma_engine *imxdma = imxdmac->imxdma;
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struct imxdma_desc *desc;
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dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%x dst_start=0x%x\n"
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" src_sgl=%s dst_sgl=%s numf=%d frame_size=%d\n", __func__,
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imxdmac->channel, xt->src_start, xt->dst_start,
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xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
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xt->numf, xt->frame_size);
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if (list_empty(&imxdmac->ld_free) ||
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imxdma_chan_is_doing_cyclic(imxdmac))
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return NULL;
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if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
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return NULL;
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desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
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desc->type = IMXDMA_DESC_INTERLEAVED;
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desc->src = xt->src_start;
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desc->dest = xt->dst_start;
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desc->x = xt->sgl[0].size;
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desc->y = xt->numf;
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desc->w = xt->sgl[0].icg + desc->x;
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desc->len = desc->x * desc->y;
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desc->direction = DMA_MEM_TO_MEM;
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desc->config_port = IMX_DMA_MEMSIZE_32;
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desc->config_mem = IMX_DMA_MEMSIZE_32;
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if (xt->src_sgl)
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desc->config_mem |= IMX_DMA_TYPE_2D;
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if (xt->dst_sgl)
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desc->config_port |= IMX_DMA_TYPE_2D;
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desc->desc.callback = NULL;
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desc->desc.callback_param = NULL;
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return &desc->desc;
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}
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static void imxdma_issue_pending(struct dma_chan *chan)
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{
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struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
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@ -825,7 +934,7 @@ static void imxdma_issue_pending(struct dma_chan *chan)
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struct imxdma_desc *desc;
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unsigned long flags;
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spin_lock_irqsave(&imxdmac->lock, flags);
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spin_lock_irqsave(&imxdma->lock, flags);
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if (list_empty(&imxdmac->ld_active) &&
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!list_empty(&imxdmac->ld_queue)) {
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desc = list_first_entry(&imxdmac->ld_queue,
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@ -840,7 +949,7 @@ static void imxdma_issue_pending(struct dma_chan *chan)
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&imxdmac->ld_active);
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}
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}
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spin_unlock_irqrestore(&imxdmac->lock, flags);
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spin_unlock_irqrestore(&imxdma->lock, flags);
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}
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static int __init imxdma_probe(struct platform_device *pdev)
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@ -903,6 +1012,13 @@ static int __init imxdma_probe(struct platform_device *pdev)
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dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
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dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
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dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
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dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
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/* Initialize 2D global parameters */
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for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
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imxdma->slots_2d[i].count = 0;
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spin_lock_init(&imxdma->lock);
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/* Initialize channel parameters */
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for (i = 0; i < IMX_DMA_CHANNELS; i++) {
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@ -923,7 +1039,6 @@ static int __init imxdma_probe(struct platform_device *pdev)
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}
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imxdmac->imxdma = imxdma;
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spin_lock_init(&imxdmac->lock);
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INIT_LIST_HEAD(&imxdmac->ld_queue);
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INIT_LIST_HEAD(&imxdmac->ld_free);
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@ -949,6 +1064,7 @@ static int __init imxdma_probe(struct platform_device *pdev)
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imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
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imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
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imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
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imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
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imxdma->dma_device.device_control = imxdma_control;
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imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
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